000 03261nam a22005415i 4500
001 978-94-007-6196-4
003 DE-He213
005 20200421112043.0
007 cr nn 008mamaa
008 130217s2013 ne | s |||| 0|eng d
020 _a9789400761964
_9978-94-007-6196-4
024 7 _a10.1007/978-94-007-6196-4
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTJFD5
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aWirnshofer, Martin.
_eauthor.
245 1 0 _aVariation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits
_h[electronic resource] /
_cby Martin Wirnshofer.
264 1 _aDordrecht :
_bSpringer Netherlands :
_bImprint: Springer,
_c2013.
300 _aXI, 83 p. 53 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSpringer Series in Advanced Microelectronics,
_x1437-0387 ;
_v41
505 0 _a1 Introduction -- 2 Sources of Variation -- 3 Related Work -- 4 Adaptive Voltage Scaling by In-situ Delay Monitoring -- 5 Design of In-situ Delay Monitors -- 6 Modeling the AVS Control Loop -- 7 Evaluation of the Pre-Error AVS Approach -- 8 Conclusion -- A Appendix -- A.1 Mathematical Derivation: Path Delay under Local Variations -- A.2 2-D DCT Transform -- References.
520 _aIncreasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted "on the fly" by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engineers interested in adaptive techniques for low-power CMOS circuits.
650 0 _aPhysics.
650 0 _aEnergy efficiency.
650 0 _aComputer simulation.
650 0 _aElectronic circuits.
650 0 _aControl engineering.
650 1 4 _aPhysics.
650 2 4 _aElectronic Circuits and Devices.
650 2 4 _aCircuits and Systems.
650 2 4 _aSimulation and Modeling.
650 2 4 _aControl.
650 2 4 _aEnergy Efficiency (incl. Buildings).
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9789400761957
830 0 _aSpringer Series in Advanced Microelectronics,
_x1437-0387 ;
_v41
856 4 0 _uhttp://dx.doi.org/10.1007/978-94-007-6196-4
912 _aZDB-2-ENG
942 _cEBK
999 _c56773
_d56773