000 04368nam a22005055i 4500
001 978-3-319-07139-8
003 DE-He213
005 20200421112045.0
007 cr nn 008mamaa
008 140823s2015 gw | s |||| 0|eng d
020 _a9783319071398
_9978-3-319-07139-8
024 7 _a10.1007/978-3-319-07139-8
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aCerny, Eduard.
_eauthor.
245 1 0 _aSVA: The Power of Assertions in SystemVerilog
_h[electronic resource] /
_cby Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny.
250 _a2nd ed. 2015.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2015.
300 _aXIX, 590 p. 173 illus.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aPart I. Opening -- Introduction -- System Verilog Language and Overview -- System Verilog Simulation Semantics -- Part II. Basic Assertions -- Assertion Statements -- Basic Properties -- Basic Sequences -- Assertion System Functions and Tasks -- Part III. Metalanguage Constructs -- Let, Sequence and Property Declarations; Inference.- Checkers -- Part IV. Advanced Assertions -- Advanced Properties -- Advanced Sequences.- Clocks -- Resets -- Procedural Concurrent Assertions.- An Apology for Local Variables -- Mechanics of Local Variables -- Recursive Properties -- Coverage -- Debugging Assertions and Efficiency Considerations -- Part V. Formal Verification -- Introduction to Assertion-Based Formal Verification.- Formal Verification and Models.- Formal Semantics.- Part VI. Advanced Checkers -- Checkers in Formal Verification.- Checker Libraries -- Appendix -- References.- Index.
520 _aThis book is a comprehensive guide to assertion-based verification of hardware designs using SystemVerilog Assertions (SVA).  It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection, and formal analysis.  The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties.  The book also shows how SVA fits into the broader SystemVerilog language, demonstrating the ways that assertions can interact with other SystemVerilog components.  The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play.  This second edition covers the features introduced by the recent IEEE 1800-2012 SystemVerilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists, and EDA tool developers.  With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.  �         Provides a comprehensive guide to assertion-based verification with SystemVerilog Assertions (SVA); �         Includes step-by-step examples of how SVA can be used to construct powerful  and reusable sets of properties; �         Covers the entire SVA language with all the recent enhancements of the IEEE 1800-2012 SystemVerilog standard.
650 0 _aEngineering.
650 0 _aMicroprocessors.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aProcessor Architectures.
650 2 4 _aElectronic Circuits and Devices.
700 1 _aDudani, Surrendra.
_eauthor.
700 1 _aHavlicek, John.
_eauthor.
700 1 _aKorchemny, Dmitry.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783319071381
856 4 0 _uhttp://dx.doi.org/10.1007/978-3-319-07139-8
912 _aZDB-2-ENG
942 _cEBK
999 _c56890
_d56890