000 03149nam a22005175i 4500
001 978-1-4614-5508-0
003 DE-He213
005 20200421112048.0
007 cr nn 008mamaa
008 120922s2013 xxu| s |||| 0|eng d
020 _a9781461455080
_9978-1-4614-5508-0
024 7 _a10.1007/978-1-4614-5508-0
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aKhan, Nauman.
_eauthor.
245 1 0 _aDesigning TSVs for 3D Integrated Circuits
_h[electronic resource] /
_cby Nauman Khan, Soha Hassoun.
264 1 _aNew York, NY :
_bSpringer New York :
_bImprint: Springer,
_c2013.
300 _aX, 76 p. 34 illus., 29 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSpringerBriefs in Electrical and Computer Engineering,
_x2191-8112
505 0 _aIntroduction -- Background -- Analysis and Mitigation of TSV-Induced Substrate Noise -- TSVs for Power Delivery -- Early Estimation of TSV Area for Power Delivery in 3-D ICs -- Carbon Nanotubes for Advancing TSV Technology -- Conclusions and Future Directions.
520 _aThis book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits.  It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks.  Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available. Finally, the authors explore the use of Carbon Nanotubes for power grid design as a futuristic alternative to Copper.
650 0 _aEngineering.
650 0 _aMicroprocessors.
650 0 _aElectronics.
650 0 _aMicroelectronics.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aProcessor Architectures.
650 2 4 _aElectronics and Microelectronics, Instrumentation.
700 1 _aHassoun, Soha.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9781461455073
830 0 _aSpringerBriefs in Electrical and Computer Engineering,
_x2191-8112
856 4 0 _uhttp://dx.doi.org/10.1007/978-1-4614-5508-0
912 _aZDB-2-ENG
942 _cEBK
999 _c57031
_d57031