000 03440nam a22004935i 4500
001 978-3-319-00681-9
003 DE-He213
005 20200421112227.0
007 cr nn 008mamaa
008 130918s2014 gw | s |||| 0|eng d
020 _a9783319006819
_9978-3-319-00681-9
024 7 _a10.1007/978-3-319-00681-9
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aSun, Guangyu.
_eauthor.
245 1 0 _aExploring Memory Hierarchy Design with Emerging Memory Technologies
_h[electronic resource] /
_cby Guangyu Sun.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2014.
300 _aVII, 122 p. 71 illus., 57 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aLecture Notes in Electrical Engineering,
_x1876-1100 ;
_v267
505 0 _aIntroduction -- Replacing Different Levels of the Memory Hierarchy with NVMs -- Moguls: a Model to Explore the Memory Hierarchy for Throughput Computing -- Exploring the Vulnerability of CMPs to Soft Errors with 3D Stacked Non-Volatile Memory.
520 _aThis book equips readers with tools for computer architecture of high performance, low power, and high reliability memory hierarchy in computer systems based on emerging memory technologies, such as STTRAM, PCM, FBDRAM, etc.  The techniques described offer advantages of high density, near-zero static power, and immunity to soft errors, which have the potential of overcoming the "memory wall."  The authors discuss memory design from various perspectives: emerging memory technologies are employed in the memory hierarchy with novel architecture modification;  hybrid memory structure is introduced to leverage advantages from multiple memory technologies; an analytical model named "Moguls" is introduced to explore quantitatively the optimization design of a memory hierarchy; finally, the vulnerability of the CMPs to radiation-based soft errors is improved by replacing different levels of on-chip memory with STT-RAMs.   �         Provides a holistic study of using emerging memory technologies in different levels of the memory hierarchy; �         Equips readers with techniques for memory design with improved performance, energy consumption, and reliability; �         Includes coverage of all memory levels, ranging from cache to storage; �         Explains how to choose the proper memory technologies in different levels of the memory hierarchy.
650 0 _aEngineering.
650 0 _aMicroprocessors.
650 0 _aSemiconductors.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aProcessor Architectures.
650 2 4 _aSemiconductors.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783319006802
830 0 _aLecture Notes in Electrical Engineering,
_x1876-1100 ;
_v267
856 4 0 _uhttp://dx.doi.org/10.1007/978-3-319-00681-9
912 _aZDB-2-ENG
942 _cEBK
999 _c57748
_d57748