000			03367nam a22004695i 4500
001			978-3-319-06838-1
003			DE-He213
005			20200421112231.0
007			cr nn 008mamaa
008			141008s2015 gw | s |||| 0|eng d
020			_a9783319068381 _9978-3-319-06838-1
024	7		_a10.1007/978-3-319-06838-1 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aGong, Lingkan. _eauthor.
245	1	0	_aFunctional Verification of Dynamically Reconfigurable FPGA-based Systems _h[electronic resource] / _cby Lingkan Gong, Oliver Diessel.
264		1	_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2015.
300			_aXXI, 216 p. 72 illus., 48 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction -- Verification Challenges -- Modeling Reconfiguration -- Getting Started with Verification -- Case Studies -- References Designs -- Conclusions.- Appendix A: Bugs Detected in Case Studies -- Appendix B: Inside the ReSim Library -- References.
520			_aThis book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric.  Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an in-depth understanding of the challenges in verifying dynamically reconfigurable systems and the state-of-the-art methods used to overcome them; Guides engineers with systematic approaches and tools to achieve verification closure in their dynamically reconfigurable projects; Includes a comprehensive set of case studies, with an analysis of real bugs detected in the designs described; Uses tools and techniques compatible with mainstream products (e.g. Xilinx/Altera tools, ModelSim simulator, Verilog/VHDL design language, etc. ...).
650		0	_aEngineering.
650		0	_aMicroprocessors.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aProcessor Architectures.
650	2	4	_aElectronic Circuits and Devices.
700	1		_aDiessel, Oliver. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783319068374
856	4	0	_uhttp://dx.doi.org/10.1007/978-3-319-06838-1
912			_aZDB-2-ENG
942			_cEBK
999			_c57997 _d57997