000 03591nam a22004935i 4500
001 978-3-319-01113-4
003 DE-He213
005 20200421112555.0
007 cr nn 008mamaa
008 131125s2014 gw | s |||| 0|eng d
020 _a9783319011134
_9978-3-319-01113-4
024 7 _a10.1007/978-3-319-01113-4
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aJavaid, Haris.
_eauthor.
245 1 0 _aPipelined Multiprocessor System-on-Chip for Multimedia
_h[electronic resource] /
_cby Haris Javaid, Sri Parameswaran.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2014.
300 _aVIII, 169 p. 40 illus., 32 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- Literature Survey -- Optimisation Framework -- Performance Estimation of Pipelined MPSoCs -- Design Space Exploration of Pipelined MPSoCs -- Adaptive Pipelined MPSoCs -- Power Management in Adaptive Pipelined MPSocs -- Multi-mode Pipelined MPSoCs -- Conclusions and Future Work.
520 _aThis book describes analytical models and estimation methods to enhance performance estimation of pipelined multiprocessor systems-on-chip (MPSoCs).  A framework is introduced for both design-time and run-time optimizations. For design space exploration, several algorithms are presented to minimize the area footprint of a pipelined MPSoC under a latency or a throughput constraint.  A novel adaptive pipelined MPSoC architecture is described, where idle processors are transitioned into low-power states at run-time to reduce energy consumption. Multi-mode pipelined MPSoCs are introduced, where multiple pipelined MPSoCs optimized separately are merged into a single pipelined MPSoC, enabling further reduction of the area footprint by sharing the processors and communication buffers. Readers will benefit from the authors' combined use of analytical models, estimation methods and exploration algorithms and will be enabled to explore billions of design points in a few minutes.   �         Describes the state-of-the-art on pipeline-level parallelism and multimedia MPSoCs; �         Includes analytical models and estimation methods for performance estimation of pipelined MPSoCs; �         Covers several design space exploration techniques for pipelined MPSoCs; �         Introduces an adaptive pipelined MPSoC with run-time processor and power managers; �         Introduces Multi-mode pipelined MPSoCs for multiple applications.    .
650 0 _aEngineering.
650 0 _aMicroprocessors.
650 0 _aElectronics.
650 0 _aMicroelectronics.
650 0 _aElectronic circuits.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aProcessor Architectures.
650 2 4 _aElectronics and Microelectronics, Instrumentation.
700 1 _aParameswaran, Sri.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9783319011127
856 4 0 _uhttp://dx.doi.org/10.1007/978-3-319-01113-4
912 _aZDB-2-ENG
942 _cEBK
999 _c59094
_d59094