000			03677nam a22004935i 4500
001			978-1-4614-8274-1
003			DE-He213
005			20200421112556.0
007			cr nn 008mamaa
008			131022s2014 xxu| s |||| 0|eng d
020			_a9781461482741 _9978-1-4614-8274-1
024	7		_a10.1007/978-1-4614-8274-1 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
245	1	0	_aRouting Algorithms in Networks-on-Chip _h[electronic resource] / _cedited by Maurizio Palesi, Masoud Daneshtalab.
264		1	_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2014.
300			_aXIV, 410 p. 219 illus., 97 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aPart I Performance Improvement -- Basic Concepts on On-Chip Networks -- A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs -- Run-Time Deadlock Detection -- The Abacus Turn Model -- Learning-based Routing Algorithms for on-Chip Networks -- Part II Multicast Communication -- Efficient and Deadlock-Free Tree-based Multicast Routing Method for Network-on-Chip -- Path-based Multicast Routing for 2D and 3D Mesh Networks -- Part III Fault Tolerance and Reliability -- Fault-Tolerant Routing Algorithms in Networks-on-Chip -- Reliable and Adaptive Algorithms for 2D and 3D Networks-on-Chip.
520			_aThis book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation.  Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.   �         Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems; �         Describes routing algorithms for NoC architectures at all abstraction levels, from the algorithmic level to actual implementation; �         Discusses the impact on NoC routing algorithms of key design objectives, such as power dissipation, energy consumption, thermal aspects, reliability, and performance.
650		0	_aEngineering.
650		0	_aMicroprocessors.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aProcessor Architectures.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
700	1		_aPalesi, Maurizio. _eeditor.
700	1		_aDaneshtalab, Masoud. _eeditor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781461482734
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4614-8274-1
912			_aZDB-2-ENG
942			_cEBK
999			_c59152 _d59152