000 | 03202nam a22005295i 4500 | ||
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001 | 978-1-4614-2410-9 | ||
003 | DE-He213 | ||
005 | 20200421112557.0 | ||
007 | cr nn 008mamaa | ||
008 | 121026s2013 xxu| s |||| 0|eng d | ||
020 |
_a9781461424109 _9978-1-4614-2410-9 |
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024 | 7 |
_a10.1007/978-1-4614-2410-9 _2doi |
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050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
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072 | 7 |
_aTEC008010 _2bisacsh |
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082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aDaněk, Martin. _eauthor. |
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245 | 1 | 0 |
_aUTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs _h[electronic resource] / _cby Martin Daněk, Leoš Kafka, Luk�aš Kohout, Jaroslav S�ykora, Roman Bartosinski. |
264 | 1 |
_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2013. |
|
300 |
_aXVIII, 222 p. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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505 | 0 | _aIntroduction -- The LEON3 Processor -- Microthreaded Extensions -- The Basic UTLEON3 Architecture.- UTLEON3 Programming by Example -- UTLEON3 Implementation Details -- Execution Effieciency of the Microthread Pipeline.- Hardware Families of Threads -- I/O and Interrupt Handling in the Microthread Mode -- The IU3 Pipeline -- Excerpts from the LEON3 Instruction Set -- Relevant LEON3 Registers and Address Space Identifiers.- Scheduler Example -- Used Resources -- Tutorial. | |
520 | _aThis book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs.  Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; Provides VHDL sources for the described processor; Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines; Includes programming by example in the micro-threaded assembly language.    . | ||
650 | 0 | _aEngineering. | |
650 | 0 | _aMicroprocessors. | |
650 | 0 | _aElectronics. | |
650 | 0 | _aMicroelectronics. | |
650 | 0 | _aElectronic circuits. | |
650 | 1 | 4 | _aEngineering. |
650 | 2 | 4 | _aCircuits and Systems. |
650 | 2 | 4 | _aProcessor Architectures. |
650 | 2 | 4 | _aElectronics and Microelectronics, Instrumentation. |
700 | 1 |
_aKafka, Leoš. _eauthor. |
|
700 | 1 |
_aKohout, Luk�aš. _eauthor. |
|
700 | 1 |
_aS�ykora, Jaroslav. _eauthor. |
|
700 | 1 |
_aBartosinski, Roman. _eauthor. |
|
710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9781461424093 |
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-1-4614-2410-9 |
912 | _aZDB-2-ENG | ||
942 | _cEBK | ||
999 |
_c59207 _d59207 |