000			03557nam a22005175i 4500
001			978-1-4614-6759-5
003			DE-He213
005			20200421112557.0
007			cr nn 008mamaa
008			130430s2013 xxu| s |||| 0|eng d
020			_a9781461467595 _9978-1-4614-6759-5
024	7		_a10.1007/978-1-4614-6759-5 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aZatt, Bruno. _eauthor.
245	1	0	_a3D Video Coding for Embedded Devices _h[electronic resource] : _bEnergy Efficient Algorithms and Architectures / _cby Bruno Zatt, Muhammad Shafique, Sergio Bampi, J�org Henkel.
264		1	_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2013.
300			_aXIX, 204 p. 126 illus., 112 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction -- Background and Related Work -- Multiview Video Coding Analysis for Energy and Quality -- Energy-Effiecient Algorithms for Multiview Video Coding -- Energy-Efficient Architectures for Multiview Video Coding -- Results and Comparison -- Conclusion and future Works.
520			_aThis book shows readers how to develop energy-efficient algorithms and hardware architectures to enable high-definition 3D video coding on resource-constrained embedded devices.  Users of the Multiview Video Coding (MVC) standard face the challenge of exploiting its 3D video-specific coding tools for increasing compression efficiency at the cost of increasing computational complexity and, consequently, the energy consumption.  This book enables readers to reduce the multiview video coding energy consumption through jointly considering the algorithmic and architectural levels.  Coverage includes an introduction to 3D videos and an extensive discussion of the current state-of-the-art of 3D video coding, as well as energy-efficient algorithms for 3D video coding and energy-efficient hardware architecture for 3D video coding.     �         Discusses challenges related to performance and power in 3D video coding for embedded devices; �         Describes energy-efficient algorithms for reducing computational complexity at multiple hierarchical levels; �         Presents energy-efficient hardware architectures along with methods for reducing on-chip and off-chip energy related to both data processing and memory access; �         Shows how to leverage jointly the algorithm and hardware architecture layers of the system.
650		0	_aEngineering.
650		0	_aMicroprocessors.
650		0	_aElectronics.
650		0	_aMicroelectronics.
650		0	_aElectronic circuits.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aElectronics and Microelectronics, Instrumentation.
650	2	4	_aProcessor Architectures.
700	1		_aShafique, Muhammad. _eauthor.
700	1		_aBampi, Sergio. _eauthor.
700	1		_aHenkel, J�org. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781461467588
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4614-6759-5
912			_aZDB-2-ENG
942			_cEBK
999			_c59217 _d59217