| 000 | 12071nam a2201381 i 4500 | ||
|---|---|---|---|
| 001 | 5263696 | ||
| 003 | IEEE | ||
| 005 | 20200421114113.0 | ||
| 006 | m o d | ||
| 007 | cr |n||||||||| | ||
| 008 | 100317t20151998nyua ob 001 0 eng d | ||
| 020 |
_a9780470545058 _qelectronic |
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| 020 |
_z9780780334298 _qprint |
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| 020 |
_z0470545054 _qelectronic |
||
| 024 | 7 |
_a10.1109/9780470545058 _2doi |
|
| 035 | _a(CaBNVSL)mat05263696 | ||
| 035 | _a(IDAMS)0b000064810c3a44 | ||
| 040 |
_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL |
||
| 050 | 4 |
_aTK7871.99.M44 _bL67 1998eb |
|
| 082 | 0 | 4 |
_a621.381/044 _222 |
| 245 | 0 | 0 |
_aLow-power CMOS design / _cedited by Anantha Chandrakasan, Robert Brodersen. |
| 264 | 1 |
_aNew York : _bIEEE Press, _cc1998. |
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| 264 | 2 |
_a[Piscataqay, New Jersey] : _bIEEE Xplore, _c[1998] |
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| 300 |
_a1 PDF (xii, 629 pages) : _billustrations. |
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| 336 |
_atext _2rdacontent |
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| 337 |
_aelectronic _2isbdmedia |
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| 338 |
_aonline resource _2rdacarrier |
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| 500 | _a"A selected reprint volume." | ||
| 504 | _aIncludes bibliographical references and indexes. | ||
| 505 | 0 | _aPreface -- OVERVIEW -- Low Power Microelectronics: Retrospect and Prospect (J. Meindl) -- Micropower IC (E. Vittoz) -- Low-Power CMOS Digital Design (A. Chandrakasan, et al.) -- CMOS Scaling for High Performance and Low-Power -- The Next Ten Years (B. Davari, et al.) -- LOW VOLTAGE TECHNOLOGIES AND CIRCUITS -- Low-Voltage Technologies and Circuits (T. Kuroda & T. Sakurai) -- Threshold Voltage Scaling and Control -- Ion-Implanted Complementary MOS Transistors in Low-Voltage Circuits (R. Swanson & J. Meindl) -- Trading Speed for Low Power by Choice of Supply and Threshold Voltages (D. Liu & C. Svensson) -- Limitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation (S. Sun & P. Tsui) -- Multiple Threshold CMOS (MTCMOS) -- 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold Voltage CMOS (S. Mutoh, et al.) -- A 1-V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application (S. Mutoh, et al.) -- Substrate Bias Controlled Variable Threshold CMOS -- 50% Active-Power Saving Without Speed Degradation Using Standby Power Reduction (SPR) Circuit (K. Seta, et al.) -- A 0.9V, 150MHz 10mW 4mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme (T. Kuroda, et al.) -- Silicon-on-Insulator Based Technologies -- SOI CMOS for Low Power Systems (D. Antoniadis) -- Back Gated CMOS on SOIAS for Dynamic Threshold Voltage Control (I. Yang, et al.) -- Design of Low Power CMOS/SOI Devices and Circuits for Memory and Signal Processing Applications (L. Thon & G. Shahidi) -- A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation (F. Assaderaghi, et al.) -- A 0.5V SIMOX-MTCMOS Circuit with 200ps Logic Gate (T. Douseki, et al.) -- EFFICIENT DC-DC CONVERSION AND ADAPTIVE POWER SUPPLY SYSTEMS -- Efficient Low Voltage DC-DC Converter Design -- A Low-Voltage CMOS DC-DC Converter for a Portable Battery-Operated System (A. Stratakos, et al.) -- Ultra Low-Power Control Circuits for PWM Converters (A. Dancy & A. Chandrakasan). | |
| 505 | 8 | _aAdaptive Power Supply Systems -- A Voltage Reduction Technique for Battery Operated Systems (V. von Kaenel, et al.) -- Automatic Adjustment of Threshold and Supply Voltage for Minimum Power Consumption in CMOS Digital Circuits (V. von Kaenel, et al.) -- Low-Power Operation Using Self-Timed Circuits and Adaptive Scaling of the Supply Voltage (L. Nielsen, et al.) -- A Low-Power Switching Power Supply for Self-Clocked Systems (G. Wei & M. Horowitz) -- Variable-Voltage Digital-Signal Processing (V. Gutnik & A. Chandrakasan) -- Scheduling for Reduced CPU Energy (M. Weiser, et al.) -- CIRCUIT AND LOGIC STYLES -- Conventional Circuit and Logic Styles -- Silicon-Gate CMOS Frequency Divider for the Electronic Wrist Watch (E. Vittoz, et al.) -- CODYMOS Frequency Dividers Achieve Low Power Consumption and High Frequency (H. Oguey & E. Vittoz) -- Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits (H. Veendrick) -- A 3.8ns CMOS 16x16 Multiplier Using Complementary Pass Transistor Logic (K. Yano, et al.) -- A High-Speed, Low-Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications (A. Parameswar, et al.) -- Static Power Driven Voltage Scaling and Delay Driven Buffer Sizing in Mixed Swing QuadRail for Sub-IV I/O Swings (R. Krishnamurthy, et al.) -- The Power Consumption of CMOS Adders and Multiliers (T. Callaway & E. Swartzlander, Jr.) -- Delay Balanced Multipliers for Low Power/Low Voltage DSP Core (T. Sakuta, et al.) -- Asynchronous Does Not Imply Low Power, But, ... (K. Van Berkel, et al.) -- Latches and Flip-Flops for Low-Power Systems (C. Svensson & J. Yuan) -- Adiabatic Logic Circuits -- Zig-Zag Path to Understanding (R. Landauer) -- A Low-Power Multiphase Circuit Technique (B. Watkins) -- Asymptotically Zero Energy Split-Level Charge Recovery Logic (S. Younis & T. Knight) -- Low Power Ditigal Systems Based on Adiabatic Switching Principles (W. Athas, et al.) -- Adiabatic Dynamic Logic (A. Dickinson & J. Denker). | |
| 505 | 8 | _aDRIVING INTERCONNECT -- Sub-1-V Swin Internal Bus Architecture for Future Low-Power ULSIs (Y. Nakagome, et al.) -- Data-Dependent Logic Swing Internal Bus Architecture for Ultra Low-Power LSIs (M. Hiraki, et al.) -- An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultra-High Data Rate ULSIs (H. Yamauchi, et al.) -- Bus-Invert Coding for Low Power I/O (M. Stan & W. Burleson) -- A Sub-CV2 Pad Driver with 10 ns Transition Time (L. Svensson, et al.) -- MEMORY CIRCUITS -- Reviews and Prospects of Low-Power Memory Circuits (K. Itoh) -- DRAM -- Trends in Low-Power RAM Circuit Technologies (K. Itoh, et al.) -- Standby/Active Mode Logic for Sub-1V Operating ULSI Memory (D. Takashima, et al.) -- A Charge Recycle Refresh for Gb-scale DRAM's in File Application (T. Kawahara, et al.) -- SRAM -- A 1-V 1-Mb SRAM for Portable Equipment (H. Morimura & N. Shibata) -- A Single Bitline Cross-Point Cell Activation (SCPA) Architecture for Ultra-Low-Power SRAMs (M. Ukita, et al.) -- Techniques to Reduce Power in Fast Wide Memories (B. Amrutur & M. Horowitz) -- A 2-ns, 5-mW, Synchronous-Powered Static-Circuit Associative TLB (H. Higuchi, et al.) -- Driving Source-Line (DSL) Cell Architecture for Sub-1-V High Speed Low Power Applications (H. Mizuno & T Nagano) -- PORTABLE TERMINAL ELECTRONICS -- General Purpose Processor Design -- Energy Dissipation in General Purpose Microprocessors (R. Gonzalez & M. Horowitz) -- Energy Efficient CMOS Microprocessor Design (T. Burd & R. Brodersen) -- A 160MHz 32b 0.5W CMOS RISC Microprocessor (J. Montanaro, et al.) -- A 320MHz, 1.5mW @ 1.35V CMOS PLL for Microprocessor Clock Generation (V. Von Kaenel, et al.) -- Dedicated and Programmable Digital Signal Processors -- A Low-Power Chipset for a Portable Multimedia I/O Terminal (A. Chandrakasan, et al.) -- A Portable Real-Time Video Decoder for Wireless Communication (T. Meng, et al.) -- Low Power Design of Memory Intensive Functions (D. Lidsky & J. Rabaey) -- A 16b Low-Power Digital Signal Processor (K. Ueda, et al.). | |
| 505 | 8 | _aA 1.8V 36mW DSP for the Half-Rate Speech CODEC (T. Shiraishi, et al.) -- Design of a 1-V Programmable DSP for Wireless Communication (P. Landman, et al.) -- Stage-Skip Pipeline: A Low Power Processor Architecture Using a Decoded Instruction Buffer (M. Hiraki, et al.) -- COMPUTER AIDED DESIGN TOOLS -- Power Analysis Techniques -- Transition Density: A New Measure of Activity in Digital Circuits (E. Najm) -- Estimation of Average Switching Activity in Combinational and Sequential Circuits (A. Ghosh, et al.) -- Power Estimation for Sequential Logic Circuits (C. Tsui, et al.) -- A Monte Carlo Approach for Power Estimation (R. Burch, et al.) -- Stratified Random Sampling for Power Estimation (C.-S. Ding, et al.) -- A Survey of High-Level Power Estimation Techniques (P. Landman) -- Activity-Sensitive Architectural Power Analysis (P. Landman & J. Rabaey) -- Power Analysis of Embedded Software: A First Step Towards Software Power Minimization (V. Tiwari, et al.) -- Power Optimization Techniques -- Technology Mapping for Low Power (V. Tiwari, et al.) -- POSE: Power Optimization and Synthesis Environment (S. Iman & M. Pedram) -- Transformation and Synthesis of FSMs fo Low-Power Gated-Clock Implementation (L. Benini & G. De Micheli) -- Precomputation-Based Sequential Logic Optimization for Low Power (M. Alidina, et al.) -- Glitch Analysis and Reduction in Register Transfer Level Power Optimization (A. Raghunathan, et al.) -- Exploiting Locality for Low-Power Design (R. Mehra, et al.) -- HYPER-LP: A System for Power Minimization Using Architectural Transformations (A. Chandrakasan, et al.) -- Variable Voltage Scheduling (S. Raje & M. Sarrafzadeh) -- System)-Level Transformations for Low Power Data Transfer and Storage (F. Catthoor, et al.) -- Author Index -- Index. | |
| 506 | 1 | _aRestricted to subscribers or individual electronic text purchasers. | |
| 530 | _aAlso available in print. | ||
| 538 | _aMode of access: World Wide Web | ||
| 588 | _aDescription based on PDF viewed 12/21/2015. | ||
| 650 | 0 |
_aMetal oxide semiconductors, Complementary _xComputer-aided design. |
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| 650 | 0 |
_aLow voltage integrated circuits _xComputer-aided design. |
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| 650 | 0 |
_aDigital integrated circuits _xComputer-aided design. |
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| 655 | 0 | _aElectronic books. | |
| 695 | _aAlgorithm design and analysis | ||
| 695 | _aAmplitude modulation | ||
| 695 | _aArrays | ||
| 695 | _aArtificial neural networks | ||
| 695 | _aBatteries | ||
| 695 | _aBoolean functions | ||
| 695 | _aBoron | ||
| 695 | _aCMOS integrated circuits | ||
| 695 | _aCMOS technology | ||
| 695 | _aCapacitance | ||
| 695 | _aClocks | ||
| 695 | _aComputational modeling | ||
| 695 | _aComputers | ||
| 695 | _aConferences | ||
| 695 | _aConverters | ||
| 695 | _aDRAM chips | ||
| 695 | _aDecoding | ||
| 695 | _aDelay | ||
| 695 | _aDigital circuits | ||
| 695 | _aDriver circuits | ||
| 695 | _aEnergy dissipation | ||
| 695 | _aEnergy measurement | ||
| 695 | _aEquations | ||
| 695 | _aFETs | ||
| 695 | _aFluctuations | ||
| 695 | _aGenerators | ||
| 695 | _aGraphics | ||
| 695 | _aImpact ionization | ||
| 695 | _aImpedance matching | ||
| 695 | _aIndexes | ||
| 695 | _aInductors | ||
| 695 | _aIntegrated circuit modeling | ||
| 695 | _aInverters | ||
| 695 | _aLatches | ||
| 695 | _aLeakage current | ||
| 695 | _aLibraries | ||
| 695 | _aLogic gates | ||
| 695 | _aMOSFET circuits | ||
| 695 | _aMOSFETs | ||
| 695 | _aMicroelectronics | ||
| 695 | _aPhysics | ||
| 695 | _aPipeline processing | ||
| 695 | _aPower demand | ||
| 695 | _aPower dissipation | ||
| 695 | _aPower supplies | ||
| 695 | _aPower transistors | ||
| 695 | _aPresses | ||
| 695 | _aProposals | ||
| 695 | _aProtocols | ||
| 695 | _aRandom access memory | ||
| 695 | _aRandom variables | ||
| 695 | _aReceivers | ||
| 695 | _aRectifiers | ||
| 695 | _aReduced instruction set computing | ||
| 695 | _aRegisters | ||
| 695 | _aSilicon | ||
| 695 | _aStochastic processes | ||
| 695 | _aStreaming media | ||
| 695 | _aSubstrates | ||
| 695 | _aSubthreshold current | ||
| 695 | _aSwitches | ||
| 695 | _aSwitching circuits | ||
| 695 | _aSystem-on-a-chip | ||
| 695 | _aThreshold voltage | ||
| 695 | _aTransistors | ||
| 695 | _aUltra large scale integration | ||
| 695 | _aVoltage control | ||
| 695 | _aVoltage measurement | ||
| 695 | _aZero voltage switching | ||
| 700 | 1 |
_aBrodersen, Robert W., _d1945- |
|
| 700 | 1 | _aChandrakasan, Anantha P. | |
| 710 | 2 |
_aJohn Wiley & Sons, _epublisher. |
|
| 710 | 2 |
_aIEEE Xplore (Online service), _edistributor. |
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| 776 | 0 | 8 |
_iPrint version: _z9780780334298 |
| 856 | 4 | 2 |
_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5263696 |
| 942 | _cEBK | ||
| 999 |
_c59432 _d59432 |
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