000			04598nam a2200937 i 4500
001			5453758
003			IEEE
005			20200421114118.0
006			m o d
007			cr |n|||||||||
008			151221s2010 njua ob 001 eng d
020			_a9780470824092 _qelectronic
020			_z9780470824078 _qprint
020			_z0470824093 _qelectronic
024	7		_a10.1002/9780470824092 _2doi
035			_a(CaBNVSL)mat05453758
035			_a(IDAMS)0b00006481237fee
040			_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL
050		4	_aTK7871.99.M44 _bK47 2009eb
082	0	4	_a621.39/5 _222
100	1		_aKer, Ming-Dou, _eauthor.
245	1	0	_aTransient-induced latchup in CMOS integrated circuits / _cMing-Dou Ker and Sheng-Fu Hsu.
264		1	_aSingapore ; _bWiley, _cc2009.
264		2	_a[Piscataqay, New Jersey] : _bIEEE Xplore, _c[2010]
300			_a1 PDF (xiii, 249 pages) : _billustrations.
336			_atext _2rdacontent
337			_aelectronic _2isbdmedia
338			_aonline resource _2rdacarrier
504			_aIncludes bibliographical references and index.
505	0		_aPhysical Mechanism of TLU under the System-Level ESD Test -- Component-Level Measurement for TLU under System-Level ESD Considerations -- TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- TLU in CMOS ICs in the Electrical Fast Transient Test -- Methodology on Extracting Compact Layout Rules for Latchup Prevention -- Special Layout Issues for Latchup Prevention -- TLU Prevention in Power-Rail ESD Clamp Circuits -- Appendix A: Practical Application Extractions of Latchup Design Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOS Process.
506	1		_aRestricted to subscribers or individual electronic text purchasers.
520			_a"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.
530			_aAlso available in print.
538			_aMode of access: World Wide Web
550			_aMade available online by Ebrary.
588			_aDescription based on PDF viewed 12/21/2015.
650		0	_aMetal oxide semiconductors, Complementary _xDefects.
650		0	_aMetal oxide semiconductors, Complementary _xReliability.
655		0	_aElectronic books.
695			_aCMOS integrated circuits
695			_aCMOS process
695			_aCMOS technology
695			_aClamps
695			_aConferences
695			_aCurrent measurement
695			_aDamping
695			_aElectric breakdown
695			_aElectrical resistance measurement
695			_aElectrostatic discharge
695			_aFrequency measurement
695			_aGuidelines
695			_aIndexes
695			_aIntegrated circuit modeling
695			_aIntegrated circuit reliability
695			_aInverters
695			_aJunctions
695			_aLayout
695			_aLogic gates
695			_aMOS devices
695			_aNoise
695			_aPerformance evaluation
695			_aPins
695			_aPulse measurements
695			_aResistance
695			_aRobustness
695			_aSemiconductor device modeling
695			_aStress
695			_aSystem-on-a-chip
695			_aTesting
695			_aThyristors
695			_aTime frequency analysis
695			_aTransient analysis
695			_aVoltage control
695			_aVoltage measurement
700	1		_aHsu, Sheng-Fu.
710	2		_aJohn Wiley & Sons, _epublisher.
710	2		_aIEEE Xplore (Online service), _edistributor.
776	0	8	_iPrint version: _z9780470824078
856	4	2	_3Abstract with links to resource _uhttp://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5453758
942			_cEBK
999			_c59642 _d59642