000			07322cam a22006378i 4500
001			ocn1089612468
003			OCoLC
005			20220711203537.0
006			m o d
007			cr cnu---unuuu
008			180804t20192019nju ob 001 0 eng
010			_a 2018037473
040			_aDLC _beng _erda _epn _cDLC _dOCLCO _dOCLCF _dOCLCQ _dN$T _dYDX _dOCLCQ _dDG1 _dYDX _dSTF _dEBLCP _dOCLCQ
019			_a1089126008 _a1089612468
020			_a9781119313977 _q(electronic book)
020			_a111931397X _q(electronic book)
020			_a9781119313984 _q(electronic book)
020			_a1119313988 _q(electronic book)
020			_a9781119313991 _q(electronic book)
020			_a1119313996 _q(electronic book)
020			_z9781119314134 _q(hardcover)
029	1		_aAU@ _b000063820646
029	1		_aAU@ _b000065126638
029	1		_aCHNEW _b001050842
029	1		_aCHVBK _b567421953
035			_a(OCoLC)1048016750 _z(OCoLC)1089126008 _z(OCoLC)1089612468
042			_apcc
050	1	4	_aTK7870.17 _b.A38 2019
072		7	_aTEC _x009070 _2bisacsh
082	0	0	_a621.39/5 _223
049			_aMAIN
245	0	0	_aAdvances in embedded and fan-out wafer level packaging technologies / _cedited by Beth Keser and Steffen Kröhnert.
264		1	_aHoboken, NJ, USA : _bJohn Wiley & Sons, Inc., _c2019.
264		4	_c©2019
300			_a1 online resource
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
504			_aIncludes bibliographical references and index.
588	0		_aOnline resource; title from digital title page (viewed on May 17, 2019).
505	0		_aPreface xvii -- List of Contributors xxiii -- Acknowledgments xxvii -- 1 History of Embedded and Fan-Out Packaging Technology 1 /Michael Topper, Andreas Ostmann, Tanja Braun, and Klaus-Dieter Lang -- 2 FO-WLP Market and Technology Trends 39 /E. Jan Vardaman -- 3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform 55 /Thorsten Meyer and Steffen Krohnert -- 4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology 77 /S.W. Yoon -- 5 NEPES Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging 97 /Jong Heon (Jay) Kim -- 6 M-Series Fan-Out with Adaptive Patterning 117 /Tim Olson and Chris Scanlan -- 7 SWIFTR Semiconductor Packaging Technology 141 /Ron Huemoeller and Curtis Zwenger -- 8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration 169 /Daquan Yu -- 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185 /Thomas Gottwald, Christian Roessle, and Alexander Neumann -- 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201 /Thomas Gottwald and Christian Roessle -- 11 Embedded Die in Substrate (Panel-Level) Packaging Technology 217 /Tomoko Takahashi and Akio Katsumata -- 12 Blade: A Chip-First Embedded Technology for Power Packaging 241 /Boris Plikat and Thorsten Scharf -- 13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology 261 /Katsushi Kan, Michiyasu Sugahara, and Markus Cichon -- 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) 271 /T. Enomoto, J.I. Matthews, and T. Motobe -- 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging 317 /Stefan Vanclooster and Dimitri Janssen -- 16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging 347 /Hugo Pristauz, Alastair Attard, and Harald Meixner -- 17 Process and Equipment for eWLB: Chip Embedding by Molding 371 /Edward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi.
505	8		_a18 Tools for Fan-Out Wafer-Level Package Processing 403 /Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung -- 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions 419 /Chris Jones, Ricardo Gaio, and Jose Castro -- 20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings 441 /Habib Hichri, Markus Arendt, and Seongkuk Lee -- 21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages 457 /Thomas Uhrmann and Boris Pova¿ay -- 22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471 /S.W. Yoon -- 23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487 /Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama -- 24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501 /Paragkumar A. Thadesar, Paul K. Jo, and Muhannad S. Bakir -- References 515 -- Index 521.
520			_aExamines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges Embedded and fan-out wafer level packaging "FO-WLP" technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons. Filled with contributions from some of the field's leading experts,??Advances in Embedded and Fan-Out Wafer Level Packaging Technologies??begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions. This valuable text: . Discusses specific company standards and their development results. Relates its content to practice as well as to contemporary and future challenges in electronics system integration and packaging Advances in Embedded and Fan-Out Wafer Level Packaging Technologies??will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research.
650		0	_aChip scale packaging. _98646
650		0	_aIntegrated circuits _xWafer-scale integration. _98647
650		7	_aTECHNOLOGY & ENGINEERING _xMechanical. _2bisacsh _98648
650		7	_aChip scale packaging. _2fast _0(OCoLC)fst00857834 _98646
650		7	_aIntegrated circuits _xWafer-scale integration. _2fast _0(OCoLC)fst00975620 _98647
655		4	_aElectronic books. _93294
700	1		_aKeser, Beth, _d1971- _eeditor. _98649
700	1		_aKroehnert, Steffen, _d1970- _eeditor. _98650
776	0	8	_iPrint version: _tAdvances in embedded and fan-out wafer level packaging technologies. _b1st edition. _dHoboken, NJ, USA : Wiley, [2018] _z9781119314134 _w(DLC) 2018034374
856	4	0	_uhttps://doi.org/10.1002/9781119313991 _zWiley Online Library
942			_cEBK
994			_aC0 _bDG1
999			_c69160 _d69160