000			04619cam a2200505Ia 4500
001			on1178633317
003			OCoLC
005			20220711203609.0
006			m d
007			cr un|---aucuu
008			200725s2020 enk ob 001 0 eng d
040			_aEBLCP _beng _cEBLCP _dYDX _dDG1
066			_c(S
019			_a1176326200
020			_a9781119751595 _q(electronic bk. : oBooks)
020			_a1119751594 _q(electronic bk. : oBooks)
020			_a9781119751571
020			_a1119751578
020			_z1786305976
020			_z9781786305978
035			_a(OCoLC)1178633317 _z(OCoLC)1176326200
050		4	_aTK7874
082	0	4	_a621.3815 _223
049			_aMAIN
100	1		_aMahdoum, Ali. _99153
245	1	0	_aCAD of circuits and integrated systems _h[electronic resource] / _cAli Mahdoum.
260			_aLondon : _bISTE Ltd. ; _aHoboken : _bWiley, _c2020.
300			_a1 online resource (293 p.)
500			_aDescription based upon print version of record.
505	8		_a1.3. Heuristics and metaheuristics -- 1.3.1. Definitions -- 1.3.2. Graph theory -- 1.3.3. Branch and bound technique -- 1.3.4. Tabu search technique -- 1.3.5. Simulated annealing technique -- 1.3.6. Genetic and evolutionary algorithms -- 1.4. Conclusion -- 2. Basic Notions on the Design of Digital Circuits and Systems -- 2.1. Introduction -- 2.2. History of VLSI circuit design -- 2.2.1. Prediffused circuit -- 2.2.2. Sea of gates -- 2.2.3. Field-programmable gate array -- FPGA -- 2.2.4. Elementary pre-characterized circuit (standard cells) -- 2.2.5. Full-custom circuit -- 2.2.6. Silicon compilation
505	8		_a2.3. System design level -- 2.3.1. Synthesis -- 2.3.2. Floorplanning -- 2.3.3. Analysis -- 2.3.4. Verification -- 2.4. Register transfer design level -- 2.4.1. Synthesis -- 2.4.2. Analysis -- 2.4.3. Verification -- 2.5. Module design level -- 2.5.1. Synthesis -- 2.5.2. Analysis -- 2.5.3. Verification -- 2.6. Gate design level -- 2.6.1. Synthesis -- 2.6.2. Analysis -- 2.6.3. Verification -- 2.7. Transistor level -- 2.7.1. NMOS and CMOS technologies -- 2.7.2. Theory of MOS transistor (current IDS) -- 2.7.3. Transfer characteristics of the inverter -- 2.7.4. Static analysis of the inverter
505	8		_a2.7.5. Threshold voltage of the inverter -- 2.7.6. Estimation of the rise and fall times of a capacitor -- 2.8. Interconnections -- 2.8.1. Synthesis of interconnections -- 2.8.2. Synthesis of networks-on-chip -- 2.9. Conclusion -- 3.Case Study: Application of Heuristics and Metaheuristics in the Design of Integrated Circuits and Systems -- 3.1. Introduction -- 3.2. System level -- 3.2.1. Synthesis of systems-on-chip (SoCs) with low energy consumption -- 3.2.2. Heuristic application to dynamic voltage and frequency scaling (DVFS) for the design of a real-time system subject to energy constraint
505	8		_a3.3. Register transfer level -- 3.3.1. Integer linear programming applied to the scheduling of operations of a data flow graph (DFG) -- 3.3.2. The scheduling of operations in a controlled data flow graph (considering the speed-power consumption tradeoff) -- 3.3.3. Efficient code assignment to the states of a finite state machine (aimed at reaching an effective control part in terms of surface, speed and power consumption)
500			_a3.3.4. Synthesis of submicron transistors and interconnections for the design of high-performance (low-power) circuits subject to power (respectively time) and surface constraints
504			_aIncludes bibliographical references and index.
590			_aJohn Wiley and Sons _bWiley Frontlist Obook All English 2020
650		0	_aIntegrated circuits _xComputer-aided design. _99154
650		0	_aComputational complexity. _93729
655		4	_aElectronic books. _93294
776	0	8	_iPrint version: _aMahdoum, Ali _tCAD of Circuits and Integrated Systems _dNewark : John Wiley & Sons, Incorporated,c2020 _z9781786305978
856	4	0	_uhttps://doi.org/10.1002/9781119751595 _zWiley Online Library
880	0		_6505-00/(S _aCover -- Half-Title Page -- Dedication -- Title Page -- Copyright Page -- Contents -- Preface -- 1. Basic Notions on Computational Complexity and Approximate Techniques -- 1.1. Computational complexity -- 1.1.1. Introduction -- 1.1.2. Big O notation -- 1.1.3. Ω Notation -- 1.1.4. Calculation of T(n) -- 1.2. Language computability -- 1.2.1. Turing machine and class P -- 1.2.2. Non-deterministic algorithm and class NP -- 1.2.3. NP-complete problems -- 1.2.4. NP-hard problems -- 1.2.5. NP-intermediate problems -- 1.2.6. Co-NP problems -- 1.2.7. Class hierarchy
942			_cEBK
994			_a92 _bDG1
999			_c69300 _d69300