000			04752cam a2200541Ia 4500
001			on1243532832
003			OCoLC
005			20220711203652.0
006			m o d
007			cr un|---aucuu
008			210327s2021 enk o 000 0 eng d
040			_aEBLCP _beng _cEBLCP _dDG1 _dOCLCO _dYDX _dUKAHL _dOCLCF
019			_a1242577731
020			_a9781119818298 _q(electronic bk. : oBook)
020			_a111981829X _q(electronic bk. : oBook)
020			_a9781119818274
020			_a1119818273
020			_z9781789450217
020			_z1789450217
029	1		_aAU@ _b000069138768
035			_a(OCoLC)1243532832 _z(OCoLC)1242577731
050		4	_aTK7895.E42
082	0	4	_a006.2/2 _223
049			_aMAIN
245	0	0	_aMulti-processor system-on-chip. _n1, _pArchitectures / _ccoordinated by Liliana Andrade, Frédéric Rousseau.
246	3	0	_aArchitectures
260			_aLondon : _bISTE, Ltd. ; _aHoboken : _bWiley, _c2021.
300			_a1 online resource (321 p.)
500			_aDescription based upon print version of record.
505	0		_aCover -- Half-Title Page -- Dedication -- Title Page -- Copyright Page -- Contents -- Foreword -- Acknowledgments -- PART 1: Processors -- 1 Processors for the Internet of Things -- 1.1. Introduction -- 1.2. Versatile processors for low-power IoT edge devices -- 1.2.1. Control processing, DSP and machine learning -- 1.2.2. Configurability and extensibility -- 1.3. Machine learning inference -- 1.3.1. Requirements for low/mid-end machine learning inference -- 1.3.2. Processor capabilities for low-power machine learning inference -- 1.3.3. A software library for machine learning inference
505	8		_a1.3.4. Example machine learning applications and benchmarks -- 1.4. Conclusion -- 1.5. References -- 2 A Qualitative Approach to Many-core Architecture -- 2.1. Introduction -- 2.2. Motivations and context -- 2.2.1. Many-core processors -- 2.2.2. Machine learning inference -- 2.2.3. Application requirements -- 2.3. The MPPA3 many-core processor -- 2.3.1. Global architecture -- 2.3.2. Compute cluster -- 2.3.3. VLIW core -- 2.3.4. Coprocessor -- 2.4. The MPPA3 software environments -- 2.4.1. High-performance computing -- 2.4.2. KaNN code generator -- 2.4.3. High-integrity computing
505	8		_a2.5. Conclusion -- 2.6. References -- 3 The Plural Many-core Architecture -- High Performance at Low Power -- 3.1. Introduction -- 3.2. Related works -- 3.3. Plural many-core architecture -- 3.4. Plural programming model -- 3.5. Plural hardware scheduler/synchronizer -- 3.6. Plural networks-on-chip -- 3.6.1. Scheduler NoC -- 3.6.2. Shared memory NoC -- 3.7. Hardware and software accelerators for the Plural architecture -- 3.8. Plural system software -- 3.9. Plural software development tools -- 3.10. Matrix multiplication algorithm on the Plural architecture
505	8		_a4 ASIP-Based Multi-Processor Systems for an Efficient Implementation of CNNs -- 4.1. Introduction -- 4.2. Related works -- 4.3. ASIP architecture -- 4.4. Single-core scaling -- 4.5. MPSoC overview -- 4.6. NoC parameter exploration -- 4.7. Summary and conclusion -- 4.8. References -- PART 2: Memory -- 5 Tackling the MPSoC DataLocality Challenge -- 5.1. Motivation -- 5.2. MPSoC target platform -- 5.3. Related work -- 5.4. Coherence-on-demand: region-based cache coherence -- 5.4.1. RBCC versus global coherence -- 5.4.2. OS extensions for coherence-on-demand -- 5.4.3. Coherency region manager
505	8		_a5.4.4. Experimental evaluations -- 5.4.5. RBCC and data placement -- 5.5. Near-memory acceleration -- 5.5.1. Near-memory synchronization accelerator -- 5.5.2. Near-memory queue management accelerator -- 5.5.3. Near-memory graph copy accelerator -- 5.5.4. Near-cache accelerator -- 5.6. The big picture -- 5.7. Conclusion -- 5.8. Acknowledgments -- 5.9. References -- 6 mMPU: Building a Memristor-based General-purpose In-memory Computation Architecture -- 6.1. Introduction -- 6.2. MAGIC NOR gate -- 6.3. In-memory algorithms for latency reduction -- 6.4. Synthesis and in-memory mapping methods
500			_a6.4.1. SIMPLE.
590			_bWiley Frontlist Obook All English 2021
650		0	_aSystems on a chip. _99801
650		0	_aMultiprocessors. _96677
650		7	_aMultiprocessors. _2fast _0(OCoLC)fst01029068 _96677
650		7	_aSystems on a chip. _2fast _0(OCoLC)fst01141473 _99801
655		4	_aElectronic books. _93294
700	1		_aAndrade, Liliana. _99802
700	1		_aRousseau, Frédéric, _d1967- _99803
776	0	8	_iPrint version: _aAndrade, Liliana _tMulti-Processor System-On-Chip 1 _dNewark : John Wiley & Sons, Incorporated,c2021 _z9781789450217
856	4	0	_uhttps://doi.org/10.1002/9781119818298 _zWiley Online Library
942			_cEBK
994			_a92 _bDG1
999			_c69510 _d69510