000			06208cam a2200637Mi 4500
001			9781315206868
003			FlBoTFG
005			20220711212155.0
006			m o d
007			cr cnu---unuuu
008			170715s2017 flu ob 001 0 eng d
040			_aOCoLC-P _beng _epn _cOCoLC-P
020			_a9781351798310 _q(electronic bk.)
020			_a1351798316 _q(electronic bk.)
020			_a9781315206868 _q(electronic bk.)
020			_a1315206862 _q(electronic bk.)
020			_a9781351798327 _q(electronic bk. : PDF)
020			_a1351798324 _q(electronic bk. : PDF)
020			_a9781351798303 _q(electronic bk. : Mobipocket)
020			_a1351798308 _q(electronic bk. : Mobipocket)
020			_z9781138032712
020			_z1138032719
035			_a(OCoLC)993766435
035			_a(OCoLC-P)993766435
050		4	_aTK7895.M4 _bB43 2017eb
072		7	_aTEC _x008090 _2bisacsh
072		7	_aTEC _x008000 _2bisacsh
072		7	_aTEC _x007000 _2bisacsh
072		7	_aTEC _x008010 _2bisacsh
072		7	_aTJFC _2bicssc
082	0	4	_a621.39732 _223
100	1		_aBhattacharyya, Arup, _eauthor. _913913
245	1	0	_aSilicon based unified memory devices and technology / _cArup Bhattacharyya.
264		1	_aBoca Raton, FL : _bCRC Press, _c[2017]
300			_a1 online resource (681 pages)
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
505	0		_aCover; Half Title; Title Page; Copyright Page; Dedication; Table of Contents; Foreword; Preface; Acknowledgments; Author; PART I Conventional Silicon Based NVM Devices; Chapter 1 Silicon Based Digital Volatile and Nonvolatile Memories: An Introductory Overview; 1.1 Digital Memories and Binary States: Basic Concepts; 1.2 Volatile Memories and NVMs; 1.2.1 Static Random Access Memory: SRAM; 1.2.2 Dynamic Random Access Memory: DRAM; 1.2.3 Read-Only Memory: ROM; 1.2.4 EPROM, EEPROM, and E2PROM; 1.2.5 Recent NVMs: NROM and NAND Flash Memories; 1.3 Memory Hierarchy in Digital Systems.
505	8		_a1.4 Fundamental Memory Concept in NVMs1.5 NVM Device Groupings and Nomenclature; References; Chapter 2 Historical Progression of NVM Devices; 2.1 Floating-Gate Devices; 2.1.1 The FAMOS Device; 2.1.2 The SAMOS Device; 2.1.3 The SAMOS 8 Kb EAROM; 2.1.4 The SIMOS Device; 2.1.5 Chronology of Floating-Gate Device Evolution; 2.1.6 The HIMOS Cell; 2.1.7 The ETOX/FLOTOX Cell; 2.1.8 The DINOR Cell; 2.1.9 The NAND Cell; 2.2 Conventional Charge-Trapping Devices; 2.2.1 MNOS/MXOS/MONOS/SNOS/SONOS; 2.2.2 Historical Evolution of MNOS, MXOS to SONOS CT Devices; 2.2.3 Evolution of CT-NVM Cell Designs.
505	8		_a2.2.3.1 Tri-Gate Memory Cell2.2.3.2 Pass Gate Memory Cell; 2.3 Nanocrystal Charge-Trapping NVM Devices; 2.3.1 Early History; 2.3.2 Nanocrystal Physics and Charge Trapping; 2.3.3 Review of Nanocrystal NVM Devices; 2.3.4 Nanocrystal Device General Characteristics; 2.3.5 Silicon Nanocrystal Device Characteristics; 2.3.6 Metal Nanocrystal Device Characteristics; 2.3.7 Germanium Nanocrystal Device Characteristics; 2.4 Direct Tunnel Memory; References; Chapter 3 General Properties of Dielectrics and Interfaces for NVM Devices; 3.0 The NVM Gate Stack Layers and Interfaces.
505	8		_a3.1 Attributes of Gate Stacks for NVM Devices3.1.1 The Energy Band of the Gate Stack Layers; 3.2 General Properties of Thin Dielectric Films; 3.2.1 Physical, Chemical, and Thermal Stability; 3.2.2 Electronic Properties; 3.2.3 Bulk and Interface Defects and Charge Trapping; 3.2.4 Charge Transport; 3.2.5 Figure of Merit for Selected Metal-Oxide Dielectric Films; 3.2.5.1 Metal Work Function and Electron Affinity; 3.3 Interfaces, Electrode Compatibility, and Process Sensitivity; 3.4 Gate Material for NVM Devices; 3.5 Dielectric Conductivity Mechanisms.
505	8		_a3.5.1 Bulk-Controlled Poole-Frenfel Mechanism3.5.2 Electrode-Controlled Quantum Mechanical Tunneling Mechanisms; 3.5.3 Direct Tunneling and/or Modified Fowler-Nordheim Tunneling; 3.5.3.1 Fowler-Nordheim Tunneling; 3.5.3.2 Enhanced Fowler-Nordheim Tunneling; 3.6 Carrier Transport Mechanisms for Multilayer Dielectrics; References; Chapter 4 Dielectric Films for NVM Devices; 4.0 Conventional Dielectric Films for NVM Devices; 4.1 Thermal Oxide: SiO2; 4.1.1 Defect Generation and Oxide Degradation; 4.1.1.1 Oxide Reliability; 4.2 CVD or LPCVD Nitride: Si3N4.
500			_a4.2.1 Nitride Traps, Trap Creation: Process and Stress Sensitivity.
520	2		_a"The primary focus of this book is on basic device concepts, memory cell design, and process technology integration. The first part provides in-depth coverage of conventional nonvolatile memory devices, stack structures from device physics, historical perspectives, and identifies limitations of conventional devices. The second part reviews advances made in reducing and/or eliminating existing limitations of NVM device parameters from the standpoint of device scalability, application extendibility, and reliability. The final part proposes multiple options of silicon based unified (nonvolatile) memory cell concepts and stack designs (SUMs). The book provides Industrial R & D personnel with the knowledge to drive the future memory technology with the established silicon FET-based establishments of their own. It explores application potentials of memory in areas such as robotics, avionics, health-industry, space vehicles, space sciences, bio-imaging, genetics etc."--Provided by publisher.
588			_aOCLC-licensed vendor bibliographic record.
650		0	_aSemiconductor storage devices _xDesign and construction. _913914
650	0	7	_aTECHNOLOGY & ENGINEERING _xElectronics _xCircuits _xGeneral. _2bisacsh _98789
650	0	7	_aTECHNOLOGY & ENGINEERING _xElectronics _xMicroelectronics. _2bisacsh _96697
650		7	_aTECHNOLOGY / Electricity _2bisacsh _913915
650		7	_aTECHNOLOGY / Electronics / General _2bisacsh _910793
650		7	_aTECHNOLOGY / Electronics / Circuits / General _2bisacsh _912515
856	4	0	_3Taylor & Francis _uhttps://www.taylorfrancis.com/books/9781315206868
856	4	2	_3OCLC metadata license agreement _uhttp://www.oclc.org/content/dam/oclc/forms/terms/vbrl-201703.pdf
942			_cEBK
999			_c70553 _d70553