000			09117nam a2201213 i 4500
001			5201491
003			IEEE
005			20220712205543.0
006			m o d
007			cr |n|||||||||
008			071115t20152007njua ob 001 0 eng d
020			_a9780470127896 _qelectronic
020			_z9780470054376 _qpaper
020			_z0470127899 _qelectronic
024	7		_a10.1002/9780470127896 _2doi
035			_a(CaBNVSL)mat05201491
035			_a(IDAMS)0b0000648104a973
040			_aCaBNVSL _beng _erda _cCaBNVSL _dCaBNVSL
050		4	_aTK7895.G36 _bK55 2007eb
082	0	4	_a621.39/5 _222
100	1		_aKilts, Steve, _d1978- _eauthor. _926050
245	1	0	_aAdvanced FPGA design : _barchitecture, implementation, and optimization / _cSteve Kilts.
264		1	_aHoboken, New Jersey : _bWiley : _cc2007.
300			_a1 PDF (xv, 336 pages) : _billustrations.
336			_atext _2rdacontent
337			_aelectronic _2isbdmedia
338			_aonline resource _2rdacarrier
504			_aIncludes bibliographical references (p. 319-320) and index.
505	0		_aPreface -- Acknowledgments -- Chapter 1. Architecting Speed -- High Throughput -- Low Latency -- Timing -- Add Register Layers -- Parallel Structures -- Flatten Logic Structures -- Register Balancing -- Reorder Paths -- Summary of Key Points -- Chapter 2. Architecting Area -- Rolling-up the Pipeline -- Control Based Logic Reuse -- Resource Sharing -- Impact of Reset on Area -- Resources without Reset -- Resources without Set -- Resources without Asynchronous Reset -- Resetting RAM -- Utilizing Set/Reset Flip-Flop Pins -- Summary of Key Points -- Chapter 3. Architecting Power -- Clock Gating -- Clock Skew -- Managing Skew -- Gated Domains -- Input Control -- Reducing the Voltage Supply -- Dual-Edge Triggered Flip-Flops -- Modifying Terminations -- Summary of Key Points -- Chapter 4. Example Design: The Advanced Encryption Standard -- AES Architectures -- Compact Architecture -- Partially Pipelined Architecture -- Fully Pipelined Architecture -- Performance versus Area -- Other Optimizations -- Chapter 5. High Level Design -- Abstract Design Techniques -- Graphical State Machines -- DSP Design -- Software/Hardware Co-Design -- Summary of Key Points -- Chapter 6. Clock Domains -- Crossing Clock Domains -- Metastability -- Solution 1: Phase Control -- Solution 2: Double-flopping -- Solution 3: FIFO Structure -- Partitioning Synchronizer Blocks -- Gated Clocks in ASIC Prototypes -- Clocks Module -- Gating Removal -- Summary of Key Points -- Chapter 7. Example Design: I2S versus SPDIF -- I2S -- Protocol -- Hardware Architecture -- Analysis -- SPDIF -- Protocol -- Hardware Architecture -- Analysis -- Chapter 8. Implementing Math Functions -- Hardware Division -- Multiply and Shift -- Iterative Division -- The Goldschmidt Method -- Taylor and Maclaurin Series Expansion -- The CORDIC Algorithm -- Summary of Key Points -- Chapter 9. Example Design: Floating Point Unit -- Floating Point Formats -- Pipelined Architecture.
505	8		_aVerilog Implementation -- Resources and Performance -- Chapter 10. Reset Circuits -- Asynchronous versus Synchronous -- Problems with Fully Asynchronous Resets -- Fully Synchronized Resets -- Asynchronous Assertion, Synchronous Deassertion -- Mixing Reset Types -- Non-Resetable Flip-Flops -- Internally Generated Resets -- Multiple Clock Domains -- Summary of Key Points -- Chapter 11. Advanced Simulation -- Testbench Architecture -- Testbench Components -- Testbench Flow -- Main Thread -- Clocks and Resets -- Testcases -- System Stimulus -- Matlab -- Bus-functional Models -- Code Coverage -- Gate Level Simulations -- Toggle Coverage -- Run-Time Traps -- Timescale -- Glitch Rejection -- Combinatorial Delay Modeling -- Summary of Key Points -- Chapter 12. Coding for Synthesis -- Decision Trees -- Priority versus Parallel -- Full Conditions -- Multiple Control Branches -- Traps -- Blocking versus Nonblocking -- For Loops -- Combinatorial Loops -- Inferred Latches -- Functions -- Design Organization -- Partitioning -- Datapath versus Control -- Clock and Reset Structures -- Multiple Instantiations -- Parameterization -- Definitions -- Parameters -- Parameters in Verilog-2001 -- Summary of Key Points -- Chapter 13. Example Design: The Secure Hash Algorithm -- SHA-1 Architecture -- Implementation Results -- Chapter 14. Synthesis Optimization -- Speed versus Area -- Resource Sharing -- Pipelining, Retiming, and Register Balancing -- The Effect of Reset on Register Balancing -- Resynchronization Registers -- FSM Compilation -- Removal of Unreachable States -- Black Boxes -- Physical Synthesis -- Forward versus Back-Annotation -- Graph Based Physical Synthesis -- Summary of Key Points -- Chapter 15. Floorplanning -- Design Partitioning -- Critical Path Floorplanning -- Floorplanning Dangers -- Optimal Floorplanning -- Data Path -- High Fan-Out -- Device Structure -- Reusability -- Reducing Power Dissipation.
505	8		_aSummary of Key Points -- Chapter 16. Place and Route Optimization -- Optimal Constraints -- Relationship between Placement and Routing -- Logic Replication -- Optimization across Hierarchy -- I/O Registers -- Pack Factor -- Mapping Logic into RAM -- Register Ordering -- Placement Seed -- Guided Place and Route -- Summary of Key Points -- Chapter 17. Example Design: Microprocessor -- SRC Architecture -- Synthesis Optimizations -- Speed versus Area -- Pipelining -- Physical Synthesis -- Floorplan Optimizations -- Partitioned Floorplan -- Critical Path Floorplan: Abstraction 1 -- Critical Path Floorplan: Abstraction 2 -- Chapter 18. Static Timing Analysis -- Standard Analysis -- Latches -- Asynchronous Circuits -- Combinatorial Feedback -- Event Driven Clocks -- Summary of Key Points -- Chapter 19. PCB Issues -- Power Supply -- Supply Requirements -- Regulation -- Decoupling Capacitors -- Concept -- Calculating Values -- Capacitor Placement -- Power Planes -- Modeling Signal Reflections -- Spice Simulations -- Configuration -- Debug -- Code Modifications -- FPGA Editor -- Placement -- Properties -- Routing -- ChipScope -- Identify -- Summary of Key Points -- Appendix A -- Appendix B -- Bibliography -- Index.
506	1		_aRestricted to subscribers or individual electronic text purchasers.
520			_aThis book provides the advanced issues of FPGA design as the underlying theme of the work. In practice, an engineer typically needs to be mentored for several years before these principles are appropriately utilized. The topics that will be discussed in this book are essential to designing FPGA's beyond moderate complexity. The goal of the book is to present practical design techniques that are otherwise only available through mentorship and real-world experience.
530			_aAlso available in print.
538			_aMode of access: World Wide Web.
588			_aDescription based on PDF viewed 12/19/2015.
650		0	_aField programmable gate arrays _xDesign and construction. _926051
655		0	_aElectronic books. _93294
695			_aAdders
695			_aAlgorithm design and analysis
695			_aAnalytical models
695			_aApproximation algorithms
695			_aApproximation methods
695			_aAutomation
695			_aBibliographies
695			_aCapacitors
695			_aClocks
695			_aComputer architecture
695			_aDecision trees
695			_aDelay
695			_aDesign automation
695			_aDigital signal processing
695			_aEncoding
695			_aEncryption
695			_aField programmable gate arrays
695			_aGenerators
695			_aHardware
695			_aHardware design languages
695			_aIEEE standards
695			_aImage edge detection
695			_aIndexes
695			_aIndustries
695			_aIterative algorithm
695			_aIterative methods
695			_aLatches
695			_aLayout
695			_aLead
695			_aLogic gates
695			_aMicroprocessors
695			_aNIST
695			_aNiobium
695			_aOptimization
695			_aPerformance evaluation
695			_aPipeline processing
695			_aPipelines
695			_aPower dissipation
695			_aPower supplies
695			_aProtocols
695			_aRadiation detectors
695			_aRails
695			_aRead only memory
695			_aReceivers
695			_aRegions
695			_aRegisters
695			_aReliability engineering
695			_aResource management
695			_aRouting
695			_aSchedules
695			_aSections
695			_aShift registers
695			_aSoftware
695			_aSynchronization
695			_aThreshold voltage
695			_aThroughput
695			_aTiming
695			_aTopology
695			_aTransient analysis
695			_aVoltage control
695			_aWire
710	2		_aIEEE Xplore (Online service), _edistributor. _926052
776	0	8	_iPrint version: _z9780470054376
856	4	2	_3Abstract with links to resource _uhttps://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5201491
942			_cEBK
999			_c73669 _d73669