000 08412nam a2201045 i 4500
001 5236707
003 IEEE
005 20220712205606.0
006 m o d
007 cr |n|||||||||
008 151221s2005 njua ob 001 eng d
020 _a9780471723004
_qebook
020 _z0471441481
_qcloth
020 _z9780471441489
_qcloth
020 _z0471723002
_qelectronic
024 7 _a10.1002/0471723002
_2doi
035 _a(CaBNVSL)mat05236707
035 _a(IDAMS)0b00006481094dc8
040 _aCaBNVSL
_beng
_erda
_cCaBNVSL
_dCaBNVSL
050 4 _aTK7885.7
_b.P37 2004eb
082 0 0 _a621.39/2
_222
100 1 _aPatma�on�aapa�on, �oTi. �aAr,
_eauthor.
_926357
245 1 0 _aDesign through Verilog HDL /
_cT.R. Padmanabhan, B. Bala Tripura Sundari.
264 1 _aPiscataway, New Jersey :
_bIEEE Press,
_cc2004.
264 2 _a[Piscataqay, New Jersey] :
_bIEEE Xplore,
_c[2005]
300 _a1 PDF (xii, 455 pages) :
_billustrations.
336 _atext
_2rdacontent
337 _aelectronic
_2isbdmedia
338 _aonline resource
_2rdacarrier
504 _aIncludes bibliographical references (p. 449-450) and index.
505 0 _aPREFACE -- ACKNOWLEDGEMENTS -- 1 INTRODUCTION TO VLSI DESIGN -- 1.1 INTRODUCTION -- 1.2 CONVENTIONAL APPROACH TO DIGITAL DESIGN -- 1.3 VLSI DESIGN -- 1.4 ASIC DESIGN FLOW -- 1.5 ROLE OF HDL -- 2 INTRODUCTION TO VERILOG -- 2.1 VERILOG AS AN HDL -- 2.2 LEVELS OF DESIGN DESCRIPTION -- 2.3 CONCURRENCY -- 2.4 SIMULATION AND SYNTHESIS -- 2.5 FUNCTIONAL VERIFICATION -- 2.6 SYSTEM TASKS -- 2.7 PROGRAMMING LANGUAGE INTERFACE (PLI) -- 2.8 MODULE -- 2.9 SIMULATION AND SYNTHESIS TOOLS -- 2.10 TEST BENCHES -- 3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG -- 3.1 INTRODUCTION -- 3.2 KEYWORDS -- 3.3 IDENTIFIERS -- 3.4 WHITE SPACE CHARACTERS -- 3.5 COMMENTS -- 3.6 NUMBERS -- 3.7 STRINGS -- 3.8 LOGIC VALUES -- 3.9 STRENGTHS -- 3.10 DATA TYPES -- 3.11 SCALARS AND VECTORS -- 3.12 PARAMETERS -- 3.13 MEMORY -- 3.14 OPERATORS -- 3.15 SYSTEM TASKS -- 3.16 EXERCISES -- 4 GATE LEVEL MODELING - 1 -- 4.1 INTRODUCTION -- 4.2 AND GATE PRIMITIVE -- 4.3 MODULE STRUCTURE -- 4.4 OTHER GATE PRIMITIVES -- 4.5 ILLUSTRATIVE EXAMPLES -- 4.6 TRI-STATE GATES -- 4.7 ARRAY OF INSTANCES OF PRIMITIVES -- 4.8 ADDITIONAL EXAMPLES -- 4.9 EXERCISES -- 5 GATE LEVEL MODELING - 2 -- 5.1 INTRODUCTION -- 5.2 DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES -- 5.3 DELAYS -- 5.4 STRENGTHS AND CONTENTION RESOLUTION -- 5.5 NET TYPES -- 5.6 DESIGN OF BASIC CIRCUITS -- 5.7 EXERCISES -- 6 MODELING AT DATA FLOW LEVEL -- 6.1 INTRODUCTION -- 6.2 CONTINUOUS ASSIGNMENT STRUCTURES -- 6.3 DELAYS AND CONTINUOUS ASSIGNMENTS -- 6.4 ASSIGNMENT TO VECTORS -- 6.5 OPERATORS -- 6.6 ADDITIONAL EXAMPLES -- 6.7 EXERCISES -- 7 BEHAVIORAL MODELING - 1 -- 7.1 INTRODUCTION -- 7.2 OPERATIONS AND ASSIGNMENTS.0 -- 7.3 FUNCTIONAL BIFURCATION.1 -- 7.4 INITIAL CONSTRUCT -- 7.5 ALWAYS CONSTRUCT -- 7.6 EXAMPLES -- 7.7 ASSIGNMENTS WITH DELAYS -- 7.8 wait CONSTRUCT -- 7.9 MULTIPLE ALWAYS BLOCKS -- 7.10 DESIGNS AT BEHAVIORAL LEVEL -- 7.11 BLOCKING AND NONBLOCKING ASSIGNMENTS -- 7.12 THE case STATEMENT -- 7.13 SIMULATION FLOW -- 7.14 EXERCISES -- 8 BEHAVIORAL MODELING II.
505 8 _a8.1 INTRODUCTION -- 8.2 if AND if-else CONSTRUCTS -- 8.3 assign-deassign CONSTRUCT -- 8.4 repeat CONSTRUCT -- 8.5 for LOOP -- 8.6 THE disable CONSTRUCT -- 8.7 while LOOP -- 8.8 forever LOOP -- 8.9 PARALLEL BLOCKS -- 8.10 force-release CONSTRUCT -- 8.11 EVENT -- 8.12 EXERCISES -- 9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES -- 9.1 INTRODUCTIUON -- 9.2 FUNCTION -- 9.3 TASKS -- 9.4 USER-DEFINED PRIMITIVES (UDP).2 -- 9.5 EXERCISES -- 10 SWITCH LEVEL MODELING 305 -- 10.1 INTRODUCTION -- 10.2 BASIC TRANSISTOR SWITCHES.5 -- 10.3 CMOS SWITCH -- 10.4 BIDIRECTIONAL GATES -- 10.5 TIME DELAYS WITH SWITCH PRIMITIVES -- 10.6 INSTANTIATIONS WITH STRENGTHS AND DELAYS -- 10.7 STRENGTH CONTENTION WITH TRIREG NETS -- 10.8 EXERCISES -- 11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES 339 -- 11.1 INTRODUCTION -- 11.2 PARAMETERS.9 -- 11.3 PATH DELAYS -- 11.4 MODULE PARAMETERS -- 11.5 SYSTEM TASKS AND FUNCTIONS -- 11.6 FILE-BASED TASKS AND FUNCTIONS -- 11.7 COMPILER DIRECTIVES -- 11.8 HIERARCHICAL ACCESS -- 11.9 GENERAL OBSERVATIONS -- 11.10 EXERCISES -- 12 QUEUES, PLAS, AND FSMS -- 12.1 INTRODUCTION -- 12.2 QUEUES -- 12.3 PROGRAMMABLE LOGIC DEVICES (PLDs) -- 12.4 DESIGN OF FINITE STATE MACHINES -- 12.5 EXERCISES -- APPENDIX A (Keywords and Their Significance) -- APPENDIX B (Truth Tables of Gates and Switches) -- REFERENCES -- INDEX.
506 1 _aRestricted to subscribers or individual electronic text purchasers.
520 _aA comprehensive resource on Verilog HDL for beginners and experts Large and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool. Describing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. Design Through Verilog HDL addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant. Other important topics covered include: . Primitives. Gate and Net delays. Buffers. CMOS switches. State machine design Further, the authors focus on illuminating the differences between gate level, data flow, and behavioral styles of Verilog, a critical distinction for designers. The book's final chapters deal with advanced topics such as timescales, parameters and related constructs, queues, and switch level design. Each chapter concludes with exercises that both ensure readers have mastered the present material and stimulate readers to explore avenues of their own choosing. Written and assembled in a paced, logical manner, Design Through Verilog HDL provides professionals, graduate students, and advanced undergraduates with a one-of-a-kind resource.
530 _aAlso available in print.
538 _aMode of access: World Wide Web
588 _aDescription based on PDF viewed 12/21/2015.
650 0 _aVerilog (Computer hardware description language)
_910611
653 _aElectrical and Electronics Engineering.
655 0 _aElectronic books.
_93294
695 _aAdders
695 _aArtificial neural networks
695 _aBibliographies
695 _aBidirectional control
695 _aBifurcation
695 _aBooks
695 _aBuffer storage
695 _aCircuit synthesis
695 _aClocks
695 _aConcurrent computing
695 _aData models
695 _aData visualization
695 _aDecoding
695 _aDelay
695 _aDelay effects
695 _aDigital circuits
695 _aDigital filters
695 _aField programmable gate arrays
695 _aFlip-flops
695 _aFlowcharts
695 _aHardware design languages
695 _aIndexes
695 _aInput variables
695 _aIntegrated circuit modeling
695 _aLatches
695 _aLogic gates
695 _aMOS devices
695 _aMOSFETs
695 _aMathematical model
695 _aMonitoring
695 _aProgrammable logic arrays
695 _aProgramming
695 _aRadiation detectors
695 _aRegisters
695 _aResistance
695 _aSimulation
695 _aSolid modeling
695 _aSwitches
695 _aSwitching circuits
695 _aTesting
695 _aVery large scale integration
695 _aWhite spaces
695 _aWire
700 1 _aTripura Sundari, B. Bala.
_926358
710 2 _aJohn Wiley & Sons,
_epublisher.
_96902
710 2 _aIEEE Xplore (Online service),
_edistributor.
_926359
776 0 8 _iPrint version:
_z9780471441489
856 4 2 _3Abstract with links to resource
_uhttps://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5236707
942 _cEBK
999 _c73748
_d73748