000 07210nam a2200589 i 4500
001 8726249
003 IEEE
005 20220712210016.0
006 m o d
007 cr |n|||||||||
008 190614s2019 mau ob 001 eng d
010 _z 2018037473 (print)
019 _a1089126008
020 _a9781119313991
_qelectronic book
020 _z9781119313977
_qelectronic book
020 _z111931397X
_qelectronic book
020 _z9781119314134
_qprint
020 _z9781119313984
_qelectronic book
020 _z1119313988
_qelectronic book
020 _z1119313996
_qelectronic book
024 7 _a10.1002/9781119313991
_2doi
035 _a(CaBNVSL)mat08726249
035 _a(IDAMS)0b0000648935c166
040 _aCaBNVSL
_beng
_erda
_cCaBNVSL
_dCaBNVSL
050 4 _aTK7870.17
_b.A38 2019eb
082 0 0 _a621.39/5
_223
245 0 0 _aAdvances in embedded and fan-out wafer level packaging technologies /
_cedited by Beth Keser and Steffen Kr�ohnert.
264 1 _aHoboken, New Jersey, USA :
_bJohn Wiley & Sons, Inc.,
_c2019.
264 2 _a[Piscataqay, New Jersey] :
_bIEEE Xplore,
_c[2019]
300 _a1 PDF (576 pages).
336 _atext
_2rdacontent
337 _aelectronic
_2isbdmedia
338 _aonline resource
_2rdacarrier
504 _aIncludes bibliographical references and index.
505 0 _aPreface xvii -- List of Contributors xxiii -- Acknowledgments xxvii -- 1 History of Embedded and Fan-Out Packaging Technology 1 /Michael Topper, Andreas Ostmann, Tanja Braun, and Klaus-Dieter Lang -- 2 FO-WLP Market and Technology Trends 39 /E. Jan Vardaman -- 3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform 55 /Thorsten Meyer and Steffen Krohnert -- 4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology 77 /S.W. Yoon -- 5 NEPES’ Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging 97 /Jong Heon (Jay) Kim -- 6 M-Series Fan-Out with Adaptive Patterning 117 /Tim Olson and Chris Scanlan -- 7 SWIFTR Semiconductor Packaging Technology 141 /Ron Huemoeller and Curtis Zwenger -- 8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration 169 /Daquan Yu -- 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185 /Thomas Gottwald, Christian Roessle, and Alexander Neumann -- 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201 /Thomas Gottwald and Christian Roessle -- 11 Embedded Die in Substrate (Panel-Level) Packaging Technology 217 /Tomoko Takahashi and Akio Katsumata -- 12 Blade: A Chip-First Embedded Technology for Power Packaging 241 /Boris Plikat and Thorsten Scharf -- 13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology 261 /Katsushi Kan, Michiyasu Sugahara, and Markus Cichon -- 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) 271 /T. Enomoto, J.I. Matthews, and T. Motobe -- 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging 317 /Stefan Vanclooster and Dimitri Janssen -- 16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging 347 /Hugo Pristauz, Alastair Attard, and Harald Meixner -- 17 Process and Equipment for eWLB: Chip Embedding by Molding 371 /Edward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi.
505 8 _a18 Tools for Fan-Out Wafer-Level Package Processing 403 /Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung -- 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions 419 /Chris Jones, Ricardo Gaio, and Jose Castro -- 20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings 441 /Habib Hichri, Markus Arendt, and Seongkuk Lee -- 21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages 457 /Thomas Uhrmann and Boris Povazay -- 22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471 /S.W. Yoon -- 23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487 /Ravi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama -- 24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501 /Paragkumar A. Thadesar, Paul K. Jo, and Muhannad S. Bakir -- References 515 -- Index 521.
506 _aRestricted to subscribers or individual electronic text purchasers.
520 _aExamines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges Embedded and fan-out wafer level packaging "FO-WLP" technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons. Filled with contributions from some of the field's leading experts,??Advances in Embedded and Fan-Out Wafer Level Packaging Technologies??begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions. This valuable text: . Discusses specific company standards and their development results. Relates its content to practice as well as to contemporary and future challenges in electronics system integration and packaging Advances in Embedded and Fan-Out Wafer Level Packaging Technologies??will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research.
530 _aAlso available in print.
538 _aMode of access: World Wide Web
588 _aDescription based on online resource; title from digital title page (viewed on May 17, 2019).
650 0 _aChip scale packaging.
_98646
650 0 _aIntegrated circuits
_xWafer-scale integration.
_98647
655 0 _aElectronic books.
_93294
700 1 _aKeser, Beth,
_d1971-
_eeditor.
_929504
700 1 _aKroehnert, Steffen,
_d1970-
_eeditor.
_929505
710 2 _aIEEE Xplore (Online Service),
_edistributor.
_929506
710 2 _aWiley,
_epublisher.
_929507
776 0 8 _iPrint version:
_tAdvances in embedded and fan-out wafer level packaging technologies.
_b1st edition.
_dHoboken, NJ, USA : Wiley, [2018]
_z9781119314134
_w(DLC) 2018034374
856 4 2 _3Abstract with links to resource
_uhttps://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=8726249
942 _cEBK
999 _c74606
_d74606