| 000 | 03929nam a22005535i 4500 | ||
|---|---|---|---|
| 001 | 978-3-319-53768-9 | ||
| 003 | DE-He213 | ||
| 005 | 20220801213446.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 170425s2017 sz | s |||| 0|eng d | ||
| 020 |
_a9783319537689 _9978-3-319-53768-9 |
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| 024 | 7 |
_a10.1007/978-3-319-53768-9 _2doi |
|
| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aRahimi, Abbas. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _932163 |
|
| 245 | 1 | 0 |
_aFrom Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators _h[electronic resource] / _cby Abbas Rahimi, Luca Benini, Rajesh K. Gupta. |
| 250 | _a1st ed. 2017. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2017. |
|
| 300 |
_aXV, 197 p. 86 illus., 48 illus. in color. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 505 | 0 | _aIntroduction -- Part 1. Predicting and Preventing Errors -- Instruction-Level Tolerance -- Sequence-Level Tolerance -- Procedure-Level Tolerance -- Kernel-Level Tolerance -- Hierarchically Focused Guardbanding -- Part 2. Detecting and Correcting Errors -- Work-Unit Tolerance -- Memristive-Based Associative Memory for Error Recovery -- Part 3. Accepting Errors -- Accuracy-Configurable OpenMP -- An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration -- Memristive-Based Associative Memory for Approximate Computational Reuse -- Spatial and Temporal Memoization -- Outlook. | |
| 520 | _aThis book focuses on computing devices and their design at various levels to combat variability. The authors provide a review of key concepts with particular emphasis on timing errors caused by various variability sources. They discuss methods to predict and prevent, detect and correct, and finally conditions under which such errors can be accepted; they also consider their implications on cost, performance and quality. Coverage includes a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software. These can be combined in various ways to achieve specific goals related to observability and controllability of the variability effects, providing means to achieve cross layer or hybrid resilience. · Covers challenges and opportunities in identifying microelectronic variability and the resulting errors at various layers in the system abstraction; · Enables readers to assess how various levels of circuit and system design can mitigate the effects of variability; · Demonstrates overall system architecture of what is now called “approximate computing” paradigm in massively parallel integrated architectures and accelerators. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
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| 650 | 0 |
_aMicroprocessors. _932164 |
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| 650 | 0 |
_aComputer architecture. _93513 |
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| 650 | 0 |
_aLogic design. _93686 |
|
| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _932165 |
| 650 | 2 | 4 |
_aProcessor Architectures. _932166 |
| 650 | 2 | 4 |
_aLogic Design. _93686 |
| 700 | 1 |
_aBenini, Luca. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _932167 |
|
| 700 | 1 |
_aGupta, Rajesh K. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _932168 |
|
| 710 | 2 |
_aSpringerLink (Online service) _932169 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319537672 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319537696 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783319852393 |
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-319-53768-9 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 942 | _cEBK | ||
| 999 |
_c75202 _d75202 |
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