| 000 | 03559nam a22005415i 4500 | ||
|---|---|---|---|
| 001 | 978-3-030-44282-8 | ||
| 003 | DE-He213 | ||
| 005 | 20220801213923.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 200504s2020 sz | s |||| 0|eng d | ||
| 020 |
_a9783030442828 _9978-3-030-44282-8 |
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| 024 | 7 |
_a10.1007/978-3-030-44282-8 _2doi |
|
| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aGoli, Mehran. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _935219 |
|
| 245 | 1 | 0 |
_aAutomated Analysis of Virtual Prototypes at the Electronic System Level _h[electronic resource] : _bDesign Understanding and Applications / _cby Mehran Goli, Rolf Drechsler. |
| 250 | _a1st ed. 2020. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2020. |
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| 300 |
_aXXI, 166 p. 53 illus. _bonline resource. |
||
| 336 |
_atext _btxt _2rdacontent |
||
| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 505 | 0 | _aChapter 1. Introduction -- Chapter 2. Background -- Chapter 3. Design Understanding Methodology -- Chapter 4. Application I: Verification -- Chapter 5. Application II: Security Validation -- Chapter 6. Application III: Design Space Exploration -- Chapter 7. Conclusion. | |
| 520 | _aThis book describes a set of SystemC‐based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration. Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL). The methodologies discussed enable readers to tackle easily key tasks and applications in the design process. Provides an extensive introduction to the field of SystemC‐based virtual prototype (VP) analysis at the electronic system level; Describes a design understanding methodology from both debugger-based and compiler‐based perspectives; Illustrates a semi‐formal verification approach to check the validity of a given VP against its specification, user‐defined rules and protocol; Discusses a security validation approach to validate the run‐time behavior of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity); Describes a design space exploration approach for SystemC-based VPs to guide designers to know under which error limits, different portions of a given VP can be approximated at different granularity levels. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
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| 650 | 0 |
_aCooperating objects (Computer systems). _96195 |
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| 650 | 0 |
_aMicroprocessors. _935220 |
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| 650 | 0 |
_aComputer architecture. _93513 |
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| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _935221 |
| 650 | 2 | 4 |
_aCyber-Physical Systems. _932475 |
| 650 | 2 | 4 |
_aProcessor Architectures. _935222 |
| 700 | 1 |
_aDrechsler, Rolf. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _91810 |
|
| 710 | 2 |
_aSpringerLink (Online service) _935223 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030442811 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030442835 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030442842 |
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-030-44282-8 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 942 | _cEBK | ||
| 999 |
_c75753 _d75753 |
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