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008 200610s2020 si | s |||| 0|eng d
020 _a9789811544057
_9978-981-15-4405-7
024 7 _a10.1007/978-981-15-4405-7
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aTaraate, Vaibbhav.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_935752
245 1 0 _aSystemVerilog for Hardware Description
_h[electronic resource] :
_bRTL Design and Verification /
_cby Vaibbhav Taraate.
250 _a1st ed. 2020.
264 1 _aSingapore :
_bSpringer Nature Singapore :
_bImprint: Springer,
_c2020.
300 _aXXI, 252 p. 104 illus., 95 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aChapter 1: Introduction to FPGA design -- Chapter 2: Introduction to HDL -- Chapter 3:Introduction to SystemVerilog -- Chapter 4: Programming using SystemVerilog -- Chapter 5:Combinational design using SystemVerilog -- Chapter 6: Sequential design using SystemVerilog -- Chapter 7: RTL design using SystemVerilog -- Chapter 8: Verification using SystemVerilog -- Chapter 9: Design Implementation using FPGA.
520 _aThis book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC.
650 0 _aElectronic circuits.
_919581
650 0 _aMicroprogramming .
_932081
650 0 _aElectronics.
_93425
650 1 4 _aElectronic Circuits and Systems.
_935753
650 2 4 _aControl Structures and Microprogramming.
_932083
650 2 4 _aElectronics and Microelectronics, Instrumentation.
_932249
710 2 _aSpringerLink (Online service)
_935754
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9789811544040
776 0 8 _iPrinted edition:
_z9789811544064
776 0 8 _iPrinted edition:
_z9789811544071
856 4 0 _uhttps://doi.org/10.1007/978-981-15-4405-7
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c75853
_d75853