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020 _a9783030713195
_9978-3-030-71319-5
024 7 _a10.1007/978-3-030-71319-5
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aMehta, Ashok B.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_936440
245 1 0 _aIntroduction to SystemVerilog
_h[electronic resource] /
_cby Ashok B. Mehta.
250 _a1st ed. 2021.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2021.
300 _aXXXV, 852 p. 156 illus., 148 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- Data Types -- Arrays -- Queues -- Structures -- Packages -- Class -- SystemVerilog 'module' -- SystemVerilog 'program' -- Interfaces -- Operators -- Constrained Random Test Generation and Verification -- SystemVerilog Assertions -- Functional Coverage -- SystemVerilog Processes -- Procedural programming statements -- Processes -- Tasks and Functions -- Clocking Blocks -- Checkers -- Inter-process communication and synchronization -- Utility System tasks and functions.
520 _aThis book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs. Provides comprehensive coverage of the entire IEEE standard SystemVerilog language; Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features; Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online; Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs. This is quite a comprehensive work. It must have taken a long time to write it. I really like that the author has taken apart each of the SystemVerilog constructs and talks about them in great detail, including example code and simulation logs. For example, there is a chapter dedicated to arrays, and another dedicated to queues - that is great to have! The Language Reference Manual (LRM) is quite dense and difficult to use as a text for learning the language. This book explains semantics at a level of detail that is not possible in an LRM. This is the strength of the book. This will be an excellent book for novice users and as a handy reference for experienced programmers. Mark Glasser Cerebras Systems.
650 0 _aElectronic circuits.
_919581
650 0 _aEmbedded computer systems.
_97792
650 0 _aMicroprocessors.
_936441
650 0 _aComputer architecture.
_93513
650 1 4 _aElectronic Circuits and Systems.
_936442
650 2 4 _aEmbedded Systems.
_932486
650 2 4 _aProcessor Architectures.
_936443
710 2 _aSpringerLink (Online service)
_936444
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783030713188
776 0 8 _iPrinted edition:
_z9783030713201
776 0 8 _iPrinted edition:
_z9783030713218
856 4 0 _uhttps://doi.org/10.1007/978-3-030-71319-5
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c75978
_d75978