| 000 | 03345nam a22005415i 4500 | ||
|---|---|---|---|
| 001 | 978-3-030-18026-3 | ||
| 003 | DE-He213 | ||
| 005 | 20220801214509.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 190522s2020 sz | s |||| 0|eng d | ||
| 020 |
_a9783030180263 _9978-3-030-18026-3 |
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| 024 | 7 |
_a10.1007/978-3-030-18026-3 _2doi |
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| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aShirinzadeh, Saeideh. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _938718 |
|
| 245 | 1 | 0 |
_aIn-Memory Computing _h[electronic resource] : _bSynthesis and Optimization / _cby Saeideh Shirinzadeh, Rolf Drechsler. |
| 250 | _a1st ed. 2020. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2020. |
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| 300 |
_aXI, 115 p. 29 illus., 12 illus. in color. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 505 | 0 | _aChapter 1: Introduction -- Chapter 2: Background -- Chapter 3: BDD Optimization and Approximation: A Multi-Criteria Approach -- Chapter 4: Synthesis for Logic-in-Memory Computing using RRAM -- Chapter 5: Compilation and Wear Le0veling for Programmable Logic-in-Memory (PLiM) Architecture -- Chapter 6: Conclusions. | |
| 520 | _aThis book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime. Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing; Describes automated compilation of programmable logic-in-memory computer architectures; Includes several effective optimization algorithm also applicable to classical logic synthesis; Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
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| 650 | 0 |
_aMicroprocessors. _938719 |
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| 650 | 0 |
_aComputer architecture. _93513 |
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| 650 | 0 |
_aElectronics. _93425 |
|
| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _938720 |
| 650 | 2 | 4 |
_aProcessor Architectures. _938721 |
| 650 | 2 | 4 |
_aElectronics and Microelectronics, Instrumentation. _932249 |
| 700 | 1 |
_aDrechsler, Rolf. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _91810 |
|
| 710 | 2 |
_aSpringerLink (Online service) _938722 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030180256 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030180270 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030180287 |
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-030-18026-3 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 942 | _cEBK | ||
| 999 |
_c76412 _d76412 |
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