| 000 | 03806nam a22005415i 4500 | ||
|---|---|---|---|
| 001 | 978-3-030-41536-5 | ||
| 003 | DE-He213 | ||
| 005 | 20220801214534.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 200320s2020 sz | s |||| 0|eng d | ||
| 020 |
_a9783030415365 _9978-3-030-41536-5 |
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| 024 | 7 |
_a10.1007/978-3-030-41536-5 _2doi |
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| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
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| 072 | 7 |
_aTEC008010 _2bisacsh |
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| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aCanelas, António Manuel Lourenço. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _938947 |
|
| 245 | 1 | 0 |
_aYield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies _h[electronic resource] / _cby António Manuel Lourenço Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta. |
| 250 | _a1st ed. 2020. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2020. |
|
| 300 |
_aXXIII, 237 p. 139 illus., 97 illus. in color. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 505 | 0 | _aIntroduction -- Analog IC Sizing Background -- Yield Estimation Techniques Related Work -- Monte Carlo-Based Yield Estimation New Methodology -- AIDA-C Variation-Aware Circuit Synthesis Tool -- Tests & Results -- Conclusion and Future Work -- Index. | |
| 520 | _aThis book presents a new methodology with reduced time impact to address the problem of analog integrated circuit (IC) yield estimation by means of Monte Carlo (MC) analysis, inside an optimization loop of a population-based algorithm. The low time impact on the overall optimization processes enables IC designers to perform yield optimization with the most accurate yield estimation method, MC simulations using foundry statistical device models considering local and global variations. The methodology described by the authors delivers on average a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. In addition to describing a newly developed yield estimation technique, the authors also provide detailed background on automatic analog IC sizing and optimization. Describes a new yield estimation methodology to reduce the time impact caused by Monte Carlo simulations, enabling its adoption in analog integrated circuits sizing and optimization processes with population-based algorithms; Enables designers to reduce the number of redesign iterations, by considering the robustness of solutions at early stages of the analog IC design flow; Includes detailed background on automatic analog IC sizing and optimization. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
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| 650 | 0 |
_aCooperating objects (Computer systems). _96195 |
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| 650 | 0 |
_aElectronics. _93425 |
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| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _938948 |
| 650 | 2 | 4 |
_aCyber-Physical Systems. _932475 |
| 650 | 2 | 4 |
_aElectronics and Microelectronics, Instrumentation. _932249 |
| 700 | 1 |
_aGuilherme, Jorge Manuel Correia. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _938949 |
|
| 700 | 1 |
_aHorta, Nuno Cavaco Gomes. _eauthor. _0(orcid)0000-0002-1687-1447 _1https://orcid.org/0000-0002-1687-1447 _4aut _4http://id.loc.gov/vocabulary/relators/aut _938950 |
|
| 710 | 2 |
_aSpringerLink (Online service) _938951 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030415358 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030415372 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030415389 |
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-030-41536-5 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 942 | _cEBK | ||
| 999 |
_c76460 _d76460 |
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