000			03242nam a22005175i 4500
001			978-3-030-03238-8
003			DE-He213
005			20220801214559.0
007			cr nn 008mamaa
008			181214s2019 sz | s |||| 0|eng d
020			_a9783030032388 _9978-3-030-03238-8
024	7		_a10.1007/978-3-030-03238-8 _2doi
050		4	_aTK7867-7867.5
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
072		7	_aTJFC _2thema
082	0	4	_a621.3815 _223
100	1		_aLee, Weng Fook. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _939195
245	1	0	_aLearning from VLSI Design Experience _h[electronic resource] / _cby Weng Fook Lee.
250			_a1st ed. 2019.
264		1	_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2019.
300			_aXXIX, 214 p. 141 illus., 55 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aChapter 1. Introduction -- Chapter 2. Design Methodology and Flow -- Chapter 3. Multiple Clock Design -- Chapter 4. Latch Inference -- Chapter 5. Design for Test -- Chapter 6. Signed Verilog -- Chapter 7. State Machine -- Chapter 8. RTL Coding Guideline -- Chapter 9. Code Coverage. .
520			_aThis book shares with readers practical design knowledge gained from the author’s 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds. Addresses practical design issues and their workarounds; Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library influence on synthesis, DFT, code coverage, state machine; Provides readers with an RTL coding guideline, based on real experience.
650		0	_aElectronic circuits. _919581
650		0	_aMicroprocessors. _939196
650		0	_aComputer architecture. _93513
650		0	_aElectronics. _93425
650	1	4	_aElectronic Circuits and Systems. _939197
650	2	4	_aProcessor Architectures. _939198
650	2	4	_aElectronics and Microelectronics, Instrumentation. _932249
710	2		_aSpringerLink (Online service) _939199
773	0		_tSpringer Nature eBook
776	0	8	_iPrinted edition: _z9783030032371
776	0	8	_iPrinted edition: _z9783030032395
856	4	0	_uhttps://doi.org/10.1007/978-3-030-03238-8
912			_aZDB-2-ENG
912			_aZDB-2-SXE
942			_cEBK
999			_c76508 _d76508