000 03150nam a22005055i 4500
001 978-981-10-8776-9
003 DE-He213
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007 cr nn 008mamaa
008 181215s2019 si | s |||| 0|eng d
020 _a9789811087769
_9978-981-10-8776-9
024 7 _a10.1007/978-981-10-8776-9
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aTaraate, Vaibbhav.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_939211
245 1 0 _aAdvanced HDL Synthesis and SOC Prototyping
_h[electronic resource] :
_bRTL Design Using Verilog /
_cby Vaibbhav Taraate.
250 _a1st ed. 2019.
264 1 _aSingapore :
_bSpringer Nature Singapore :
_bImprint: Springer,
_c2019.
300 _aXXI, 307 p. 263 illus., 196 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level.
520 _aThis book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.
650 0 _aElectronic circuits.
_919581
650 0 _aMicroprogramming .
_932081
650 0 _aLogic design.
_93686
650 1 4 _aElectronic Circuits and Systems.
_939212
650 2 4 _aControl Structures and Microprogramming.
_932083
650 2 4 _aLogic Design.
_93686
710 2 _aSpringerLink (Online service)
_939213
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9789811087752
776 0 8 _iPrinted edition:
_z9789811087776
856 4 0 _uhttps://doi.org/10.1007/978-981-10-8776-9
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c76511
_d76511