000 03661nam a22005535i 4500
001 978-3-030-30596-3
003 DE-He213
005 20220801215047.0
007 cr nn 008mamaa
008 191122s2020 sz | s |||| 0|eng d
020 _a9783030305963
_9978-3-030-30596-3
024 7 _a10.1007/978-3-030-30596-3
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aFarahmandi, Farimah.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_942098
245 1 0 _aSystem-on-Chip Security
_h[electronic resource] :
_bValidation and Verification /
_cby Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra.
250 _a1st ed. 2020.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2020.
300 _aXIX, 289 p. 105 illus., 78 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- Security Verification Using Formal Methods -- Simulation-Based Security Validation Approaches -- Security Validation Using Side-Channel Analysis -- Automated Vulnerability Detection And Mitigation -- Conclusion.
520 _aThis book describes a wide variety of System-on-Chip (SoC) security threats and vulnerabilities, as well as their sources, in each stage of a design life cycle. The authors discuss a wide variety of state-of-the-art security verification and validation approaches such as formal methods and side-channel analysis, as well as simulation-based security and trust validation approaches. This book provides a comprehensive reference for system on chip designers and verification and validation engineers interested in verifying security and trust of heterogeneous SoCs. Outlines a wide variety of hardware security threats and vulnerabilities as well as their sources in each of the stages of a design life cycle; Summarizes unsafe current design practices that lead to security and trust vulnerabilities; Covers state-of-the-art techniques as well as ongoing research efforts in developing scalable security validation using formal methods including symbolic algebra, model checkers, SAT solvers, and theorem provers; Explains how to leverage security validation approaches to prevent side-channel attacks; Presents automated debugging and patching techniques in the presence of security vulnerabilities; Includes case studies for security validation of arithmetic circuits, controller designs, as well as processor-based SoCs.
650 0 _aElectronic circuits.
_919581
650 0 _aMicroprocessors.
_942099
650 0 _aComputer architecture.
_93513
650 0 _aElectronics.
_93425
650 1 4 _aElectronic Circuits and Systems.
_942100
650 2 4 _aProcessor Architectures.
_942101
650 2 4 _aElectronics and Microelectronics, Instrumentation.
_932249
700 1 _aHuang, Yuanwen.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_942102
700 1 _aMishra, Prabhat.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_942103
710 2 _aSpringerLink (Online service)
_942104
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783030305956
776 0 8 _iPrinted edition:
_z9783030305970
776 0 8 _iPrinted edition:
_z9783030305987
856 4 0 _uhttps://doi.org/10.1007/978-3-030-30596-3
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c77065
_d77065