| 000 | 03834nam a22005415i 4500 | ||
|---|---|---|---|
| 001 | 978-3-030-31310-4 | ||
| 003 | DE-He213 | ||
| 005 | 20220801215416.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 191220s2020 sz | s |||| 0|eng d | ||
| 020 |
_a9783030313104 _9978-3-030-31310-4 |
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| 024 | 7 |
_a10.1007/978-3-030-31310-4 _2doi |
|
| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 072 | 7 |
_aTJFC _2thema |
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| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aManna, Kanchan. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _944188 |
|
| 245 | 1 | 0 |
_aDesign and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures _h[electronic resource] / _cby Kanchan Manna, Jimson Mathew. |
| 250 | _a1st ed. 2020. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2020. |
|
| 300 |
_aXII, 162 p. 31 illus., 8 illus. in color. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 505 | 0 | _aIntroduction to Network-on-Chip Designs and Tests -- Iterative Mapping with Through Silicon Via (TSV) placement for 3D-NoC-based multicore systems -- A constructive Heuristic for integrated mapping and TSV Placement for 3D-NoC-based multicore systems -- Discrete Particle Swarm Optimization for integrated mapping and TSV Placement for 3D-NoC-based multicore systems -- Temperature-aware application mapping strategy for 2D-NoC-based multicore systems -- Temperature-aware design strategy for 3D-NoC-based multicore systems -- Temperature-aware test strategy for 2D as well as 3D-NoC-based multicore systems. | |
| 520 | _aThis book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications. Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems; Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems; Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
|
| 650 | 0 |
_aMicroprocessors. _944189 |
|
| 650 | 0 |
_aComputer architecture. _93513 |
|
| 650 | 0 |
_aElectronics. _93425 |
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| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _944190 |
| 650 | 2 | 4 |
_aProcessor Architectures. _944191 |
| 650 | 2 | 4 |
_aElectronics and Microelectronics, Instrumentation. _932249 |
| 700 | 1 |
_aMathew, Jimson. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _944192 |
|
| 710 | 2 |
_aSpringerLink (Online service) _944193 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030313098 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030313111 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030313128 |
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-030-31310-4 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 942 | _cEBK | ||
| 999 |
_c77458 _d77458 |
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