000 04150nam a22005895i 4500
001 978-3-319-60402-2
003 DE-He213
005 20220801215635.0
007 cr nn 008mamaa
008 170706s2018 sz | s |||| 0|eng d
020 _a9783319604022
_9978-3-319-60402-2
024 7 _a10.1007/978-3-319-60402-2
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aMeinerzhagen, Pascal.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_945584
245 1 0 _aGain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
_h[electronic resource] /
_cby Pascal Meinerzhagen, Adam Teman, Robert Giterman, Noa Edri, Andreas Burg, Alexander Fish.
250 _a1st ed. 2018.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2018.
300 _aIX, 146 p. 84 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aMotivation -- Introduction to Gain-Cell Based eDRAMs (GC-eDRAMs) -- GC-eDRAMs Operated at Scaled Supply Voltages -- Near-VT GC-eDRAM Implementations with Extended Retention Times -- Aggressive Technology and Voltage Scaling (to Sub-VT Domain) -- Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications -- 4T Gain-Cell with Internal-Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes -- Multilevel GC-eDRAM (MLGC-eDRAM) -- Soft Error Tolerant Low Power 4T Gain-Cell Array with Multi-Bit Error Detection and Correction -- Conclusions.
520 _aThis book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
650 0 _aElectronic circuits.
_919581
650 0 _aComputer storage devices.
_95655
650 0 _aMemory management (Computer science).
_920025
650 0 _aElectronics.
_93425
650 1 4 _aElectronic Circuits and Systems.
_945585
650 2 4 _aComputer Memory Structure.
_943894
650 2 4 _aElectronics and Microelectronics, Instrumentation.
_932249
700 1 _aTeman, Adam.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_945586
700 1 _aGiterman, Robert.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_945587
700 1 _aEdri, Noa.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_945588
700 1 _aBurg, Andreas.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_945589
700 1 _aFish, Alexander.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_945590
710 2 _aSpringerLink (Online service)
_945591
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783319604015
776 0 8 _iPrinted edition:
_z9783319604039
776 0 8 _iPrinted edition:
_z9783319868554
856 4 0 _uhttps://doi.org/10.1007/978-3-319-60402-2
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c77704
_d77704