000 | 03306nam a22005655i 4500 | ||
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001 | 978-3-319-75465-9 | ||
003 | DE-He213 | ||
005 | 20220801215727.0 | ||
007 | cr nn 008mamaa | ||
008 | 180418s2018 sz | s |||| 0|eng d | ||
020 |
_a9783319754659 _9978-3-319-75465-9 |
||
024 | 7 |
_a10.1007/978-3-319-75465-9 _2doi |
|
050 | 4 | _aTK7867-7867.5 | |
072 | 7 |
_aTJFC _2bicssc |
|
072 | 7 |
_aTEC008010 _2bisacsh |
|
072 | 7 |
_aTJFC _2thema |
|
082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aChampac, Victor. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _946107 |
|
245 | 1 | 0 |
_aTiming Performance of Nanometer Digital Circuits Under Process Variations _h[electronic resource] / _cby Victor Champac, Jose Garcia Gervacio. |
250 | _a1st ed. 2018. | ||
264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2018. |
|
300 |
_aXVIII, 185 p. 116 illus., 91 illus. in color. _bonline resource. |
||
336 |
_atext _btxt _2rdacontent |
||
337 |
_acomputer _bc _2rdamedia |
||
338 |
_aonline resource _bcr _2rdacarrier |
||
347 |
_atext file _bPDF _2rda |
||
490 | 1 |
_aFrontiers in Electronic Testing ; _v39 |
|
505 | 0 | _aIntroduction -- Mathematical Fundamentals -- Process Variations -- Gate delay under process variations -- Path Delay Under Process Variations -- Circuit Analysis under Process Variations -- FinFET Technology and design issues. | |
520 | _aThis book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level “design hints” are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability. | ||
650 | 0 |
_aElectronic circuits. _919581 |
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650 | 0 |
_aMicroprocessors. _946108 |
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650 | 0 |
_aComputer architecture. _93513 |
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650 | 0 |
_aElectronics. _93425 |
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650 | 1 | 4 |
_aElectronic Circuits and Systems. _946109 |
650 | 2 | 4 |
_aProcessor Architectures. _946110 |
650 | 2 | 4 |
_aElectronics and Microelectronics, Instrumentation. _932249 |
700 | 1 |
_aGarcia Gervacio, Jose. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _946111 |
|
710 | 2 |
_aSpringerLink (Online service) _946112 |
|
773 | 0 | _tSpringer Nature eBook | |
776 | 0 | 8 |
_iPrinted edition: _z9783319754642 |
776 | 0 | 8 |
_iPrinted edition: _z9783319754666 |
776 | 0 | 8 |
_iPrinted edition: _z9783030092399 |
830 | 0 |
_aFrontiers in Electronic Testing ; _v39 _946113 |
|
856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-319-75465-9 |
912 | _aZDB-2-ENG | ||
912 | _aZDB-2-SXE | ||
942 | _cEBK | ||
999 |
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