000 04165nam a22005415i 4500
001 978-3-030-40786-5
003 DE-He213
005 20220801215944.0
007 cr nn 008mamaa
008 201215s2021 sz | s |||| 0|eng d
020 _a9783030407865
_9978-3-030-40786-5
024 7 _a10.1007/978-3-030-40786-5
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aLevi, Itamar.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_947460
245 1 0 _aDual Mode Logic
_h[electronic resource] :
_bA New Paradigm for Digital IC Design /
_cby Itamar Levi, Alexander Fish.
250 _a1st ed. 2021.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2021.
300 _aXIV, 185 p. 111 illus., 68 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aChapter 1. Introduction -- Chapter 2. Introduction to Dual Mode Logic (DML) -- Chapter 3. Optimization of DML Gates -- Chapter 4. Low Voltage DML -- Chapter 5. DML Energy-Delay Tradeoffs and Optimization -- Chapter 6. DML Control -- Chapter 7. Towards a DML Library Characterization and Design with Standard Flow -- Chapter 8. Towards a DML Optimized Synthesis -- Chapter 9. Dual Mode Logic in FD-SOI Technology. Chapter 10. Conclusion.
520 _aThis book presents Dual Mode Logic (DML), a new design paradigm for digital integrated circuits. DML logic gates can operate in two modes, each optimized for a different metric. Its on-the-fly switching between these operational modes at the gate, block and system levels provide maximal E-D optimization flexibility. Each highly detailed chapter has multiple illustrations showing how the DML paradigm seamlessly implements digital circuits that dissipate less energy while simultaneously improving performance and reducing area without a significant compromise in reliability. All the facets of the DML methodology are covered, starting from basic concepts, through single gate optimization, general module optimization, design trade-offs and new ways DML can be integrated into standard design flows using standard EDA tools. DML logic is compatible with numerous applications but is particularly advantageous for ultra-low power, reliable high performance systems, and advanced scaled technologies Written in language accessible to students and design engineers, each topic is oriented toward immediate application by all those interested in an alternative to CMOS logic. Describes a novel, promising alternative to conventional CMOS logic, known as Dual Mode Logic (DML), with which a single gate can be operated selectively in two modes, each optimized for a different metric (e.g., energy consumption, performance, size); Demonstrates several techniques at the architectural level, which can result in high energy savings and improved system performance; Focuses on the tradeoffs between power, area and speed including optimizations at the transistor and gate level, including alternatives to DML basic cells; Illustrates DML efficiency for a variety of VLSI applications.
650 0 _aElectronic circuits.
_919581
650 0 _aLogic design.
_93686
650 0 _aMicroprocessors.
_947461
650 0 _aComputer architecture.
_93513
650 1 4 _aElectronic Circuits and Systems.
_947462
650 2 4 _aLogic Design.
_93686
650 2 4 _aProcessor Architectures.
_947463
700 1 _aFish, Alexander.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_947464
710 2 _aSpringerLink (Online service)
_947465
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783030407858
776 0 8 _iPrinted edition:
_z9783030407872
776 0 8 _iPrinted edition:
_z9783030407889
856 4 0 _uhttps://doi.org/10.1007/978-3-030-40786-5
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c78046
_d78046