000			03947nam a22005415i 4500
001			978-3-030-69209-4
003			DE-He213
005			20220801220145.0
007			cr nn 008mamaa
008			210419s2021 sz | s |||| 0|eng d
020			_a9783030692094 _9978-3-030-69209-4
024	7		_a10.1007/978-3-030-69209-4 _2doi
050		4	_aTK7895.E42
072		7	_aUKM _2bicssc
072		7	_aTEC008010 _2bisacsh
072		7	_aUKM _2thema
082	0	4	_a006.22 _223
100	1		_aHuhn, Sebastian. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _948656
245	1	0	_aDesign for Testability, Debug and Reliability _h[electronic resource] : _bNext Generation Measures Using Formal Techniques / _cby Sebastian Huhn, Rolf Drechsler.
250			_a1st ed. 2021.
264		1	_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2021.
300			_aXXI, 164 p. 47 illus., 25 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aIntroduction -- Integrated Circuits -- Formal Techniques -- Embedded Compression Architecture for Test Access Ports -- Optimization SAT-based Retargeting for Embedded Compression -- Reconfigurable TAP Controllers with Embedded Compression -- Embedded Multichannel Test Compression for Low-Pin Count Test -- Enhanced Reliability using Formal Techniques -- Conclusion and Outlook.
520			_aThis book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces. Provides readers with a combination of a comprehensive set of formal techniques covering and enhancing different aspects of the state-of-the-art design and test flow for ICs; Introduces newly developed heuristic, formal optimization-based and partition-based retargeting techniques and integrates them into a common framework; Describes fully compliant (with respect to industrial de-facto standard) measures to enhance the DFT, DFD and DFR capabilities while supporting standardized data exchange formats; Includes new measures to tackle shortcomings of existing state-of-the-art methods, including zero-defect enforcing safety-critical applications.
650		0	_aEmbedded computer systems. _97792
650		0	_aElectronic circuit design. _94185
650		0	_aMicroprocessors. _948657
650		0	_aComputer architecture. _93513
650	1	4	_aEmbedded Systems. _932486
650	2	4	_aElectronics Design and Verification. _938529
650	2	4	_aProcessor Architectures. _948658
700	1		_aDrechsler, Rolf. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _91810
710	2		_aSpringerLink (Online service) _948659
773	0		_tSpringer Nature eBook
776	0	8	_iPrinted edition: _z9783030692087
776	0	8	_iPrinted edition: _z9783030692100
776	0	8	_iPrinted edition: _z9783030692117
856	4	0	_uhttps://doi.org/10.1007/978-3-030-69209-4
912			_aZDB-2-ENG
912			_aZDB-2-SXE
942			_cEBK
999			_c78265 _d78265