000 03324nam a22005295i 4500
001 978-3-319-48899-8
003 DE-He213
005 20220801220731.0
007 cr nn 008mamaa
008 161130s2017 sz | s |||| 0|eng d
020 _a9783319488998
_9978-3-319-48899-8
024 7 _a10.1007/978-3-319-48899-8
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aPosser, Gracieli.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_952050
245 1 0 _aElectromigration Inside Logic Cells
_h[electronic resource] :
_bModeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS /
_cby Gracieli Posser, Sachin S. Sapatnekar, Ricardo Reis.
250 _a1st ed. 2017.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2017.
300 _aXX, 118 p. 72 illus., 69 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aChapter 1. Introduction -- Chapter 2. State of the Art -- Chapter 3. Modeling Cell-internal EM -- Chapter 4. Current Calculation -- Chapter 5. Experimental Setup -- Chapter 6.Results -- Chapter 7. Analyzing the Electromigration Effects on Different Metal Layers -- Chapter 8. Conclusions.
520 _aThis book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics. .
650 0 _aElectronic circuits.
_919581
650 0 _aMicroprocessors.
_952051
650 0 _aComputer architecture.
_93513
650 1 4 _aElectronic Circuits and Systems.
_952052
650 2 4 _aProcessor Architectures.
_952053
700 1 _aSapatnekar, Sachin S.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_952054
700 1 _aReis, Ricardo.
_eauthor.
_0(orcid)0000-0001-5781-5858
_1https://orcid.org/0000-0001-5781-5858
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_952055
710 2 _aSpringerLink (Online service)
_952056
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783319488981
776 0 8 _iPrinted edition:
_z9783319489001
776 0 8 _iPrinted edition:
_z9783319840413
856 4 0 _uhttps://doi.org/10.1007/978-3-319-48899-8
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c78879
_d78879