000 04306nam a22005295i 4500
001 978-3-319-30539-4
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008 160413s2016 sz | s |||| 0|eng d
020 _a9783319305394
_9978-3-319-30539-4
024 7 _a10.1007/978-3-319-30539-4
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aMehta, Ashok B.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_952086
245 1 0 _aSystemVerilog Assertions and Functional Coverage
_h[electronic resource] :
_bGuide to Language, Methodology and Applications /
_cby Ashok B. Mehta.
250 _a2nd ed. 2016.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2016.
300 _aXXXV, 406 p. 247 illus., 9 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _aIntroduction -- System Verilog Assertions -- Immediate Assertions -- Concurrent Assertions – Basics (sequence, property, assert) -- Sampled Value Functions $rose, $fell -- Operators -- System Functions and Tasks -- Multiple clocks -- Local Variables -- Recursive property -- Detecting and using endpoint of a sequence -- ‘expect’ -- ‘assume’ and formal (static functional) verification -- Other important topics -- Asynchronous Assertions !!! -- IEEE-1800–2009 Features -- SystemVerilog Assertions LABs -- System Verilog Assertions – LAB Answers -- Functional Coverage -- Performance Implications of coverage methodology -- Coverage Options.
520 _aThis book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SystemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification using SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug. This updated second edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures. · Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics; · Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage language and methodologies; · Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; · Explains each concept in a step-by-step fashion and applies it to a practical real life example; · Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.
650 0 _aElectronic circuits.
_919581
650 0 _aElectronics.
_93425
650 0 _aMicroprocessors.
_952087
650 0 _aComputer architecture.
_93513
650 1 4 _aElectronic Circuits and Systems.
_952088
650 2 4 _aElectronics and Microelectronics, Instrumentation.
_932249
650 2 4 _aProcessor Architectures.
_952089
710 2 _aSpringerLink (Online service)
_952090
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783319305387
776 0 8 _iPrinted edition:
_z9783319305400
776 0 8 _iPrinted edition:
_z9783319808338
856 4 0 _uhttps://doi.org/10.1007/978-3-319-30539-4
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c78886
_d78886