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020 _a9789811085543
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024 7 _a10.1007/978-981-10-8554-3
_2doi
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072 7 _aTEC008010
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082 0 4 _a621.3815
_223
100 1 _aHaj-Yahya, Jawad.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_953922
245 1 0 _aEnergy Efficient High Performance Processors
_h[electronic resource] :
_bRecent Approaches for Designing Green High Performance Computing /
_cby Jawad Haj-Yahya, Avi Mendelson, Yosi Ben Asher, Anupam Chattopadhyay.
250 _a1st ed. 2018.
264 1 _aSingapore :
_bSpringer Nature Singapore :
_bImprint: Springer,
_c2018.
300 _aXIV, 165 p. 73 illus., 68 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aComputer Architecture and Design Methodologies,
_x2367-3486
505 0 _aIntroduction -- Background -- DOEE: Dynamic Optimization framework for better Energy Efficiency -- Fine-grain Power Breakdown of Modern Out-Of-Order Cores and its implications on Skylake based systems -- Compiler-Directed Power Management for Superscalars -- SEEM: Symbolic Execution for Energy Modeling -- Related Works -- Conclusions and Future Work.
520 _aThis book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM). Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.
650 0 _aElectronic circuits.
_919581
650 0 _aMicroprocessors.
_953923
650 0 _aComputer architecture.
_93513
650 1 4 _aElectronic Circuits and Systems.
_953924
650 2 4 _aProcessor Architectures.
_953925
700 1 _aMendelson, Avi.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_953926
700 1 _aBen Asher, Yosi.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_953927
700 1 _aChattopadhyay, Anupam.
_eauthor.
_0(orcid)0000-0002-8818-6983
_1https://orcid.org/0000-0002-8818-6983
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_953928
710 2 _aSpringerLink (Online service)
_953929
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
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776 0 8 _iPrinted edition:
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776 0 8 _iPrinted edition:
_z9789811341847
830 0 _aComputer Architecture and Design Methodologies,
_x2367-3486
_953930
856 4 0 _uhttps://doi.org/10.1007/978-981-10-8554-3
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