000 04078nam a22005535i 4500
001 978-3-319-74382-0
003 DE-He213
005 20220801221338.0
007 cr nn 008mamaa
008 180314s2018 sz | s |||| 0|eng d
020 _a9783319743820
_9978-3-319-74382-0
024 7 _a10.1007/978-3-319-74382-0
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aBuccella, Pietro.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_955504
245 1 0 _aParasitic Substrate Coupling in High Voltage Integrated Circuits
_h[electronic resource] :
_bMinority and Majority Carriers Propagation in Semiconductor Substrate /
_cby Pietro Buccella, Camillo Stefanucci, Maher Kayal, Jean-Michel Sallese.
250 _a1st ed. 2018.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2018.
300 _aXVII, 183 p. 124 illus., 73 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aAnalog Circuits and Signal Processing,
_x2197-1854
505 0 _aChapter1: Overview of Parasitic Substrate Coupling -- Chapter2: Design Challenges in High Voltage ICs -- Chapter3: Substrate Modeling with Parasitic Transistors -- Chapter4: TCAD Validation of the Model -- Chapter5: Extraction Tool for the Substrate Network -- Chapter6: Parasitic Bipolar Transistors in Benchmark Structures -- Chapter7: Substrate Coupling Analysis and Evaluation of Protection Strategies.
520 _aThis book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools. The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits. The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis. Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits; Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate; Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices; Offers design guidelines to reduce couplings by adding specific test protections.
650 0 _aElectronic circuits.
_919581
650 0 _aElectronics.
_93425
650 1 4 _aElectronic Circuits and Systems.
_955505
650 2 4 _aElectronics and Microelectronics, Instrumentation.
_932249
700 1 _aStefanucci, Camillo.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_955506
700 1 _aKayal, Maher.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_955507
700 1 _aSallese, Jean-Michel.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_955508
710 2 _aSpringerLink (Online service)
_955509
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783319743813
776 0 8 _iPrinted edition:
_z9783319743837
776 0 8 _iPrinted edition:
_z9783030089764
830 0 _aAnalog Circuits and Signal Processing,
_x2197-1854
_955510
856 4 0 _uhttps://doi.org/10.1007/978-3-319-74382-0
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c79569
_d79569