000 03670nam a22005535i 4500
001 978-3-319-34060-9
003 DE-He213
005 20220801222102.0
007 cr nn 008mamaa
008 160720s2017 sz | s |||| 0|eng d
020 _a9783319340609
_9978-3-319-34060-9
024 7 _a10.1007/978-3-319-34060-9
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aMartins, Ricardo.
_eauthor.
_0(orcid)0000-0002-8251-1415
_1https://orcid.org/0000-0002-8251-1415
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_959624
245 1 0 _aAnalog Integrated Circuit Design Automation
_h[electronic resource] :
_bPlacement, Routing and Parasitic Extraction Techniques /
_cby Ricardo Martins, Nuno Lourenço, Nuno Horta.
250 _a1st ed. 2017.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2017.
300 _aXVI, 207 p. 108 illus., 79 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
505 0 _a1 Introduction -- 2 State-of-the-Art on Analog Layout Automation -- 3 AIDA-L: Architecture and Integration -- 4 Template-based Placer -- 5 Optimization-based Placer -- 6 Fully-Automatic Router -- 7 Empirical-based Parasitic Extractor -- 8 Experimental Results -- 9 Conclusions and Future Work.
520 _aThis book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures; Includes evolutionary multi-objective multi-constraint detailed Router; Enables parasitic extraction performed over a semi-complete layout.
650 0 _aElectronic circuits.
_919581
650 0 _aMicroprocessors.
_959625
650 0 _aComputer architecture.
_93513
650 0 _aElectronics.
_93425
650 1 4 _aElectronic Circuits and Systems.
_959626
650 2 4 _aProcessor Architectures.
_959627
650 2 4 _aElectronics and Microelectronics, Instrumentation.
_932249
700 1 _aLourenço, Nuno.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_959628
700 1 _aHorta, Nuno.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_959629
710 2 _aSpringerLink (Online service)
_959630
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783319340593
776 0 8 _iPrinted edition:
_z9783319340616
776 0 8 _iPrinted edition:
_z9783319816685
856 4 0 _uhttps://doi.org/10.1007/978-3-319-34060-9
912 _aZDB-2-ENG
912 _aZDB-2-SXE
942 _cEBK
999 _c80382
_d80382