000 | 03178nam a22005295i 4500 | ||
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001 | 978-3-319-43174-1 | ||
003 | DE-He213 | ||
005 | 20220801222721.0 | ||
007 | cr nn 008mamaa | ||
008 | 160802s2017 sz | s |||| 0|eng d | ||
020 |
_a9783319431741 _9978-3-319-43174-1 |
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024 | 7 |
_a10.1007/978-3-319-43174-1 _2doi |
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072 | 7 |
_aTJFC _2bicssc |
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_aTEC008010 _2bisacsh |
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_aTJFC _2thema |
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_a621.3815 _223 |
100 | 1 |
_aAmaru, Luca Gaetano. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _962963 |
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245 | 1 | 0 |
_aNew Data Structures and Algorithms for Logic Synthesis and Verification _h[electronic resource] / _cby Luca Gaetano Amaru. |
250 | _a1st ed. 2017. | ||
264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2017. |
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300 |
_aXVI, 156 p. 44 illus., 20 illus. in color. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
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505 | 0 | _aIntroduction -- Part 1. Logic Representation, Manipulation and Optimization -- Biconditional Logic -- Majority Logic -- Part 2. Logic Satisfiability and Equivalence Checking -- Exploiting Logic Properties to Speedup SAT -- Majority Normal Form Representation and Satisfiability -- Improvements to the Equivalence Checking of Reversible Circuits -- Conclusions. | |
520 | _aThis book introduces new logic primitives for electronic design automation tools. The author approaches fundamental EDA problems from a different, unconventional perspective, in order to demonstrate the key role of rethinking EDA solutions in overcoming technological limitations of present and future technologies. The author discusses techniques that improve the efficiency of logic representation, manipulation and optimization tasks by taking advantage of majority and biconditional logic primitives. Readers will be enabled to accelerate formal methods by studying core properties of logic circuits and developing new frameworks for logic reasoning engines. · Provides a comprehensive, theoretical study on majority and biconditional logic for logic synthesis; · Updates the current scenario in synthesis and verification – especially in light of emerging technologies; · Demonstrates applications to CMOS technology and emerging technologies. | ||
650 | 0 |
_aElectronic circuits. _919581 |
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650 | 0 |
_aMicroprocessors. _962964 |
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650 | 0 |
_aComputer architecture. _93513 |
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650 | 0 |
_aLogic design. _93686 |
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650 | 1 | 4 |
_aElectronic Circuits and Systems. _962965 |
650 | 2 | 4 |
_aProcessor Architectures. _962966 |
650 | 2 | 4 |
_aLogic Design. _93686 |
710 | 2 |
_aSpringerLink (Online service) _962967 |
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773 | 0 | _tSpringer Nature eBook | |
776 | 0 | 8 |
_iPrinted edition: _z9783319431734 |
776 | 0 | 8 |
_iPrinted edition: _z9783319431758 |
776 | 0 | 8 |
_iPrinted edition: _z9783319827537 |
856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-319-43174-1 |
912 | _aZDB-2-ENG | ||
912 | _aZDB-2-SXE | ||
942 | _cEBK | ||
999 |
_c81078 _d81078 |