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020 _a9783031798559
_9978-3-031-79855-9
024 7 _a10.1007/978-3-031-79855-9
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072 7 _aTBC
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082 0 4 _a620
_223
100 1 _aYanushkevich, Svetlana N.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_978878
245 1 0 _aIntroduction to Noise-Resilient Computing
_h[electronic resource] /
_cby Svetlana N. Yanushkevich, Seiya Kasai, Golam Tangim, A.H. Tran.
250 _a1st ed. 2013.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2013.
300 _aXIX, 132 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSynthesis Lectures on Digital Circuits & Systems,
_x1932-3174
505 0 _aIntroduction to probabilistic computation models -- Nanoscale circuits and fluctuation problems -- Estimators and Metrics -- MRF Models of Logic Gates -- Neuromorphic models -- Noise-tolerance via error correcting -- Conclusion and future work.
520 _aNoise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MRF model by a new type of binary decision diagram (BDD), called a cyclic BDD. In this approach, logic gates and circuits are designed using 2-to-1 bi-directional switches. Such circuits are often modeled using Shannon expansions with the corresponding graph-based implementation, BDDs. Simulation experiments are reported to show the noise immunity of the proposed structures. Audiences who may benefit from this lecture include graduate students taking classes on advanced computing device design, and academic and industrial researchers. Table of Contents: Introduction to probabilistic computation models / Nanoscale circuits and fluctuation problems / Estimators and Metrics / MRF Models of Logic Gates / Neuromorphic models / Noise-tolerance via error correcting / Conclusion and future work.
650 0 _aEngineering.
_99405
650 0 _aElectronic circuits.
_919581
650 0 _aControl engineering.
_931970
650 0 _aRobotics.
_92393
650 0 _aAutomation.
_92392
650 0 _aComputers.
_98172
650 1 4 _aTechnology and Engineering.
_978879
650 2 4 _aElectronic Circuits and Systems.
_978880
650 2 4 _aControl, Robotics, Automation.
_931971
650 2 4 _aComputer Hardware.
_933420
700 1 _aKasai, Seiya.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_978881
700 1 _aTangim, Golam.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_978882
700 1 _aTran, A.H.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_978883
710 2 _aSpringerLink (Online service)
_978884
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783031798542
776 0 8 _iPrinted edition:
_z9783031798566
830 0 _aSynthesis Lectures on Digital Circuits & Systems,
_x1932-3174
_978885
856 4 0 _uhttps://doi.org/10.1007/978-3-031-79855-9
912 _aZDB-2-SXSC
942 _cEBK
999 _c84674
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