| 000 | 03635nam a22005175i 4500 | ||
|---|---|---|---|
| 001 | 978-3-031-01733-9 | ||
| 003 | DE-He213 | ||
| 005 | 20240730163550.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 221028s2011 sz | s |||| 0|eng d | ||
| 020 |
_a9783031017339 _9978-3-031-01733-9 |
||
| 024 | 7 |
_a10.1007/978-3-031-01733-9 _2doi |
|
| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aSorin, Daniel. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _979245 |
|
| 245 | 1 | 2 |
_aA Primer on Memory Consistency and Cache Coherence _h[electronic resource] / _cby Daniel Sorin, Mark Hill, David Wood. |
| 250 | _a1st ed. 2011. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2011. |
|
| 300 |
_aIV, 212 p. _bonline resource. |
||
| 336 |
_atext _btxt _2rdacontent |
||
| 337 |
_acomputer _bc _2rdamedia |
||
| 338 |
_aonline resource _bcr _2rdacarrier |
||
| 347 |
_atext file _bPDF _2rda |
||
| 490 | 1 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 |
|
| 505 | 0 | _aPreface -- Introduction to Consistency and Coherence -- Coherence Basics -- Memory Consistency Motivation and Sequential Consistency -- Total Store Order and the x86 Memory Model -- Relaxed Memory Consistency -- Coherence Protocols -- Snooping Coherence Protocols -- Directory Coherence Protocols -- Advanced Topics in Coherence -- Author Biographies. | |
| 520 | _aMany modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
|
| 650 | 0 |
_aMicroprocessors. _979246 |
|
| 650 | 0 |
_aComputer architecture. _93513 |
|
| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _979247 |
| 650 | 2 | 4 |
_aProcessor Architectures. _979248 |
| 700 | 1 |
_aHill, Mark. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _979249 |
|
| 700 | 1 |
_aWood, David. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _979250 |
|
| 710 | 2 |
_aSpringerLink (Online service) _979251 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031006050 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031028618 |
| 830 | 0 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 _979252 |
|
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-031-01733-9 |
| 912 | _aZDB-2-SXSC | ||
| 942 | _cEBK | ||
| 999 |
_c84744 _d84744 |
||