000 | 04128nam a22005175i 4500 | ||
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001 | 978-3-031-01729-2 | ||
003 | DE-He213 | ||
005 | 20240730163653.0 | ||
007 | cr nn 008mamaa | ||
008 | 220601s2011 sz | s |||| 0|eng d | ||
020 |
_a9783031017292 _9978-3-031-01729-2 |
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024 | 7 |
_a10.1007/978-3-031-01729-2 _2doi |
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050 | 4 | _aTK7867-7867.5 | |
072 | 7 |
_aTJFC _2bicssc |
|
072 | 7 |
_aTEC008010 _2bisacsh |
|
072 | 7 |
_aTJFC _2thema |
|
082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aGonzalez, Antonio. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _979848 |
|
245 | 1 | 0 |
_aProcessor Microarchitecture _h[electronic resource] : _bAn Implementation Perspective / _cby Antonio Gonzalez, Fernando Latorre, Grigorios Magklis. |
250 | _a1st ed. 2011. | ||
264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2011. |
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300 |
_aX, 106 p. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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347 |
_atext file _bPDF _2rda |
||
490 | 1 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 |
|
505 | 0 | _aIntroduction -- Caches -- The Instruction Fetch Unit -- Decode -- Allocation -- The Issue Stage -- Execute -- The Commit Stage -- References -- Author Biographies. | |
520 | _aThis lecture presents a study of the microarchitecture of contemporary microprocessors. The focus is on implementation aspects, with discussions on their implications in terms of performance, power, and cost of state-of-the-art designs. The lecture starts with an overview of the different types of microprocessors and a review of the microarchitecture of cache memories. Then, it describes the implementation of the fetch unit, where special emphasis is made on the required support for branch prediction. The next section is devoted to instruction decode with special focus on the particular support to decoding x86 instructions. The next chapter presents the allocation stage and pays special attention to the implementation of register renaming. Afterward, the issue stage is studied. Here, the logic to implement out-of-order issue for both memory and non-memory instructions is thoroughly described. The following chapter focuses on the instruction execution and describes the different functional units that can be found in contemporary microprocessors, as well as the implementation of the bypass network, which has an important impact on the performance. Finally, the lecture concludes with the commit stage, where it describes how the architectural state is updated and recovered in case of exceptions or misspeculations. This lecture is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture. It is also intended for practitioners in the industry in the area of microprocessor design. The book assumes that the reader is familiar with the main concepts regarding pipelining, out-of-order execution, cache memories, and virtual memory. Table of Contents: Introduction / Caches / The Instruction Fetch Unit / Decode / Allocation / The Issue Stage / Execute / The Commit Stage / References / Author Biographies. | ||
650 | 0 |
_aElectronic circuits. _919581 |
|
650 | 0 |
_aMicroprocessors. _979849 |
|
650 | 0 |
_aComputer architecture. _93513 |
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650 | 1 | 4 |
_aElectronic Circuits and Systems. _979850 |
650 | 2 | 4 |
_aProcessor Architectures. _979851 |
700 | 1 |
_aLatorre, Fernando. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _979852 |
|
700 | 1 |
_aMagklis, Grigorios. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _979853 |
|
710 | 2 |
_aSpringerLink (Online service) _979854 |
|
773 | 0 | _tSpringer Nature eBook | |
776 | 0 | 8 |
_iPrinted edition: _z9783031006012 |
776 | 0 | 8 |
_iPrinted edition: _z9783031028571 |
830 | 0 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 _979855 |
|
856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-031-01729-2 |
912 | _aZDB-2-SXSC | ||
942 | _cEBK | ||
999 |
_c84860 _d84860 |