| 000 | 03724nam a22005175i 4500 | ||
|---|---|---|---|
| 001 | 978-3-031-01734-6 | ||
| 003 | DE-He213 | ||
| 005 | 20240730163653.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 220601s2011 sz | s |||| 0|eng d | ||
| 020 |
_a9783031017346 _9978-3-031-01734-6 |
||
| 024 | 7 |
_a10.1007/978-3-031-01734-6 _2doi |
|
| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aBalasubramonian, Rajeev. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _979856 |
|
| 245 | 1 | 0 |
_aMulti-Core Cache Hierarchies _h[electronic resource] / _cby Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar. |
| 250 | _a1st ed. 2011. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2011. |
|
| 300 |
_aXVI, 137 p. _bonline resource. |
||
| 336 |
_atext _btxt _2rdacontent |
||
| 337 |
_acomputer _bc _2rdamedia |
||
| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
||
| 490 | 1 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 |
|
| 505 | 0 | _aBasic Elements of Large Cache Design -- Organizing Data in CMP Last Level Caches -- Policies Impacting Cache Hit Rates -- Interconnection Networks within Large Caches -- Technology -- Concluding Remarks. | |
| 520 | _aA key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints. The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, and practitioners who wish to understand the landscape of recent cache research. The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers. Table of Contents: Basic Elements of Large Cache Design / Organizing Data in CMP Last Level Caches / Policies Impacting Cache Hit Rates / Interconnection Networks within Large Caches / Technology / Concluding Remarks. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
|
| 650 | 0 |
_aMicroprocessors. _979857 |
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| 650 | 0 |
_aComputer architecture. _93513 |
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| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _979858 |
| 650 | 2 | 4 |
_aProcessor Architectures. _979859 |
| 700 | 1 |
_aJouppi, Norman P. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _979860 |
|
| 700 | 1 |
_aMuralimanohar, Naveen. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _979861 |
|
| 710 | 2 |
_aSpringerLink (Online service) _979862 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031006067 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031028625 |
| 830 | 0 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 _979863 |
|
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-031-01734-6 |
| 912 | _aZDB-2-SXSC | ||
| 942 | _cEBK | ||
| 999 |
_c84861 _d84861 |
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