| 000 | 03178nam a22005055i 4500 | ||
|---|---|---|---|
| 001 | 978-3-031-01763-6 | ||
| 003 | DE-He213 | ||
| 005 | 20240730163716.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 220601s2019 sz | s |||| 0|eng d | ||
| 020 |
_a9783031017636 _9978-3-031-01763-6 |
||
| 024 | 7 |
_a10.1007/978-3-031-01763-6 _2doi |
|
| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aBalasubramonian, Rajeev. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _980098 |
|
| 245 | 1 | 0 |
_aInnovations in the Memory System _h[electronic resource] / _cby Rajeev Balasubramonian. |
| 250 | _a1st ed. 2019. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2019. |
|
| 300 |
_aXXI, 129 p. _bonline resource. |
||
| 336 |
_atext _btxt _2rdacontent |
||
| 337 |
_acomputer _bc _2rdamedia |
||
| 338 |
_aonline resource _bcr _2rdacarrier |
||
| 347 |
_atext file _bPDF _2rda |
||
| 490 | 1 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 |
|
| 505 | 0 | _aList of Figures -- List of Tables -- Preface -- Acknowledgments -- Introduction -- Memory System Basics for Every Architect -- Commercial Memory Products -- Memory Scheduling -- Data Placement -- Memory Chip Microarchitectures -- Memory Channels -- Memory Reliability -- Memory Refresh -- Near Data Processing -- Memory Security -- Closing Thoughts -- Bibliography -- Author's Biography. | |
| 520 | _aThe memory system has the potential to be a hub for future innovation. While conventional memory systems focused primarily on high density, other memory system metrics like energy, security, and reliability are grabbing modern research headlines. With processor performance stagnating, it is also time to consider new programming models that move some application computations into the memory system. This, in turn, will lead to feature-rich memory systems with new interfaces. The past decade has seen a number of memory system innovations that point to this future where the memory system will be much more than dense rows of unintelligent bits. This book takes a tour through recent and prominent research works, touching upon new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
|
| 650 | 0 |
_aMicroprocessors. _980099 |
|
| 650 | 0 |
_aComputer architecture. _93513 |
|
| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _980100 |
| 650 | 2 | 4 |
_aProcessor Architectures. _980101 |
| 710 | 2 |
_aSpringerLink (Online service) _980102 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031000607 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031006357 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031028915 |
| 830 | 0 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 _980103 |
|
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-031-01763-6 |
| 912 | _aZDB-2-SXSC | ||
| 942 | _cEBK | ||
| 999 |
_c84899 _d84899 |
||