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020 _a9783031792052
_9978-3-031-79205-2
024 7 _a10.1007/978-3-031-79205-2
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aGogte, Vaibhav.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_981649
245 1 2 _aA Primer on Memory Persistency
_h[electronic resource] /
_cby Vaibhav Gogte, Aasheesh Kolli, Thomas F. Wenisch.
250 _a1st ed. 2022.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2022.
300 _aXIX, 95 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSynthesis Lectures on Computer Architecture,
_x1935-3243
505 0 _aPreface -- Acknowledgments -- Persistent Memories -- Data Persistence -- Memory Persistency Models -- Hardware Mechanisms for Atomic Durability -- Programming Persistent Memory Systems -- Conclusion -- Bibliography -- Authors' Biographies.
520 _aThis book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface. Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures andprogram crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages. These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors.
650 0 _aElectronic circuits.
_919581
650 0 _aMicroprocessors.
_981650
650 0 _aComputer architecture.
_93513
650 1 4 _aElectronic Circuits and Systems.
_981651
650 2 4 _aProcessor Architectures.
_981652
700 1 _aKolli, Aasheesh.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_981653
700 1 _aWenisch, Thomas F.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_981654
710 2 _aSpringerLink (Online service)
_981655
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783031792175
776 0 8 _iPrinted edition:
_z9783031791932
776 0 8 _iPrinted edition:
_z9783031792298
830 0 _aSynthesis Lectures on Computer Architecture,
_x1935-3243
_981656
856 4 0 _uhttps://doi.org/10.1007/978-3-031-79205-2
912 _aZDB-2-SXSC
942 _cEBK
999 _c85217
_d85217