| 000 | 03567nam a22005175i 4500 | ||
|---|---|---|---|
| 001 | 978-3-031-01728-5 | ||
| 003 | DE-He213 | ||
| 005 | 20240730164220.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 220601s2010 sz | s |||| 0|eng d | ||
| 020 |
_a9783031017285 _9978-3-031-01728-5 |
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| 024 | 7 |
_a10.1007/978-3-031-01728-5 _2doi |
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| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aHarris, Tim. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _982990 |
|
| 245 | 1 | 0 |
_aTransactional Memory, Second Edition _h[electronic resource] / _cby Tim Harris, James Larus, Ravi Rajwar. |
| 250 | _a2nd ed. 2010. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2010. |
|
| 300 |
_aXV, 247 p. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
||
| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
||
| 490 | 1 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 |
|
| 505 | 0 | _aIntroduction -- Basic Transactions -- Building on Basic Transactions -- Software Transactional Memory -- Hardware-Supported Transactional Memory -- Conclusions. | |
| 520 | _aThe advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically - either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, to a language runtime system, or to hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early spring 2010. Table of Contents: Introduction / Basic Transactions / Building on Basic Transactions / Software Transactional Memory / Hardware-Supported Transactional Memory / Conclusions. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
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| 650 | 0 |
_aMicroprocessors. _982991 |
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| 650 | 0 |
_aComputer architecture. _93513 |
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| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _982993 |
| 650 | 2 | 4 |
_aProcessor Architectures. _982995 |
| 700 | 1 |
_aLarus, James. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _982996 |
|
| 700 | 1 |
_aRajwar, Ravi. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _982997 |
|
| 710 | 2 |
_aSpringerLink (Online service) _983000 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031006005 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031028564 |
| 830 | 0 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 _983001 |
|
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-031-01728-5 |
| 912 | _aZDB-2-SXSC | ||
| 942 | _cEBK | ||
| 999 |
_c85438 _d85438 |
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