| 000 | 03748nam a22004935i 4500 | ||
|---|---|---|---|
| 001 | 978-3-031-01746-9 | ||
| 003 | DE-He213 | ||
| 005 | 20240730164221.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 220601s2015 sz | s |||| 0|eng d | ||
| 020 |
_a9783031017469 _9978-3-031-01746-9 |
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| 024 | 7 |
_a10.1007/978-3-031-01746-9 _2doi |
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| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
|
| 072 | 7 |
_aTEC008010 _2bisacsh |
|
| 072 | 7 |
_aTJFC _2thema |
|
| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aHughes, Christopher J. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _983014 |
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| 245 | 1 | 0 |
_aSingle-Instruction Multiple-Data Execution _h[electronic resource] / _cby Christopher J. Hughes. |
| 250 | _a1st ed. 2015. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2015. |
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| 300 |
_aXVI, 105 p. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 490 | 1 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 |
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| 505 | 0 | _aPreface -- Acknowledgments -- Data Parallelism -- Exploiting Data Parallelism with SIMD Execution -- Computation and Control Flow -- Memory Operations -- Horizontal Operations -- Conclusions -- Bibliography -- Author's Biography . | |
| 520 | _aHaving hit power limitations to even more aggressive out-of-order execution in processor cores, many architects in the past decade have turned to single-instruction-multiple-data (SIMD) execution to increase single-threaded performance. SIMD execution, or having a single instruction drive execution of an identical operation on multiple data items, was already well established as a technique to efficiently exploit data parallelism. Furthermore, support for it was already included in many commodity processors. However, in the past decade, SIMD execution has seen a dramatic increase in the set of applications using it, which has motivated big improvements in hardware support in mainstream microprocessors. The easiest way to provide a big performance boost to SIMD hardware is to make it wider-i.e., increase the number of data items hardware operates on simultaneously. Indeed, microprocessor vendors have done this. However, as we exploit more data parallelism in applications, certain challenges can negatively impact performance. In particular, conditional execution, non-contiguous memory accesses, and the presence of some dependences across data items are key roadblocks to achieving peak performance with SIMD execution. This book first describes data parallelism, and why it is so common in popular applications. We then describe SIMD execution, and explain where its performance and energy benefits come from compared to other techniques to exploit parallelism. Finally, we describe SIMD hardware support in current commodity microprocessors. This includes both expected design tradeoffs, as well as unexpected ones, as we work to overcome challenges encountered when trying to map real software to SIMD execution. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
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| 650 | 0 |
_aMicroprocessors. _983016 |
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| 650 | 0 |
_aComputer architecture. _93513 |
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| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _983019 |
| 650 | 2 | 4 |
_aProcessor Architectures. _983020 |
| 710 | 2 |
_aSpringerLink (Online service) _983021 |
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| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031006180 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031028748 |
| 830 | 0 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 _983022 |
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| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-031-01746-9 |
| 912 | _aZDB-2-SXSC | ||
| 942 | _cEBK | ||
| 999 |
_c85442 _d85442 |
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