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001 978-3-031-01751-3
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020 _a9783031017513
_9978-3-031-01751-3
024 7 _a10.1007/978-3-031-01751-3
_2doi
050 4 _aTK7867-7867.5
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
072 7 _aTJFC
_2thema
082 0 4 _a621.3815
_223
100 1 _aSardashti, Somayeh.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_983040
245 1 2 _aA Primer on Compression in the Memory Hierarchy
_h[electronic resource] /
_cby Somayeh Sardashti, Angelos Arelakis, Per Stenström, David A. Wood.
250 _a1st ed. 2016.
264 1 _aCham :
_bSpringer International Publishing :
_bImprint: Springer,
_c2016.
300 _aXVIII, 70 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSynthesis Lectures on Computer Architecture,
_x1935-3243
505 0 _aList of Figures -- List of Tables -- Preface -- Acknowledgments -- Introduction -- Compression Algorithms -- Cache Compression -- Memory Compression -- Cache/Memory Link Compression -- Concluding Remarks -- References -- Authors' Biographies .
520 _aThis synthesis lecture presents the current state-of-the-art in applying low-latency, lossless hardware compression algorithms to cache, memory, and the memory/cache link. There are many non-trivial challenges that must be addressed to make data compression work well in this context. First, since compressed data must be decompressed before it can be accessed, decompression latency ends up on the critical memory access path. This imposes a significant constraint on the choice of compression algorithms. Second, while conventional memory systems store fixed-size entities like data types, cache blocks, and memory pages, these entities will suddenly vary in size in a memory system that employs compression. Dealing with variable size entities in a memory system using compression has a significant impact on the way caches are organized and how to manage the resources in main memory. We systematically discuss solutions in the open literature to these problems. Chapter 2 provides the foundations of data compression by first introducing the fundamental concept of value locality. We then introduce a taxonomy of compression algorithms and show how previously proposed algorithms fit within that logical framework. Chapter 3 discusses the different ways that cache memory systems can employ compression, focusing on the trade-offs between latency, capacity, and complexity of alternative ways to compact compressed cache blocks. Chapter 4 discusses issues in applying data compression to main memory and Chapter 5 covers techniques for compressing data on the cache-to-memory links. This book should help a skilled memory system designer understand the fundamental challenges in applying compression to the memory hierarchy and introduce him/her to the state-of-the-art techniques in addressing them.
650 0 _aElectronic circuits.
_919581
650 0 _aMicroprocessors.
_983041
650 0 _aComputer architecture.
_93513
650 1 4 _aElectronic Circuits and Systems.
_983043
650 2 4 _aProcessor Architectures.
_983045
700 1 _aArelakis, Angelos.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_983047
700 1 _aStenström, Per.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_983048
700 1 _aWood, David A.
_eauthor.
_4aut
_4http://id.loc.gov/vocabulary/relators/aut
_983050
710 2 _aSpringerLink (Online service)
_983054
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783031006234
776 0 8 _iPrinted edition:
_z9783031028793
830 0 _aSynthesis Lectures on Computer Architecture,
_x1935-3243
_983055
856 4 0 _uhttps://doi.org/10.1007/978-3-031-01751-3
912 _aZDB-2-SXSC
942 _cEBK
999 _c85445
_d85445