| 000 | 03796nam a22005895i 4500 | ||
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| 001 | 978-3-031-02031-5 | ||
| 003 | DE-He213 | ||
| 005 | 20240730164633.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 220601s2016 sz | s |||| 0|eng d | ||
| 020 |
_a9783031020315 _9978-3-031-02031-5 |
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| 024 | 7 |
_a10.1007/978-3-031-02031-5 _2doi |
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| 050 | 4 | _aT1-995 | |
| 072 | 7 |
_aTBC _2bicssc |
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| 082 | 0 | 4 |
_a620 _223 |
| 100 | 1 |
_aGimenez, Salvador Pinillos. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _985461 |
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| 245 | 1 | 0 |
_aLayout Techniques in MOSFETs _h[electronic resource] / _cby Salvador Pinillos Gimenez. |
| 250 | _a1st ed. 2016. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2016. |
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| 300 |
_aXI, 69 p. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 490 | 1 |
_aSynthesis Lectures on Emerging Engineering Technologies, _x2381-1439 |
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| 505 | 0 | _aDedication -- Acknowledgments -- Introduction -- The Origin of the Innovative Layout Techniques for MOSFETS -- Diamond MOSFET (Hexagonal Gate Geometry) -- Octo Layout Style (Octagonal Gate Shape) for MOSFET -- Ellipsoidal Layout Style for MOSFET -- Fish Layout Style (". | |
| 520 | _aThis book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach. | ||
| 650 | 0 |
_aEngineering. _99405 |
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_aElectrical engineering. _985463 |
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_aElectronic circuits. _919581 |
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_aComputers. _98172 |
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| 650 | 0 |
_aMaterials science. _95803 |
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_aSurfaces (Technology). _910743 |
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| 650 | 0 |
_aThin films. _97674 |
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| 650 | 1 | 4 |
_aTechnology and Engineering. _985466 |
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_aElectrical and Electronic Engineering. _985468 |
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_aElectronic Circuits and Systems. _985470 |
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_aComputer Hardware. _933420 |
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_aMaterials Science. _95803 |
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_aSurfaces, Interfaces and Thin Film. _931793 |
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_aSpringerLink (Online service) _985474 |
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| 773 | 0 | _tSpringer Nature eBook | |
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_iPrinted edition: _z9783031009037 |
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_iPrinted edition: _z9783031031595 |
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_aSynthesis Lectures on Emerging Engineering Technologies, _x2381-1439 _985476 |
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| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-031-02031-5 |
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