| 000 | 03750nam a22005535i 4500 | ||
|---|---|---|---|
| 001 | 978-3-031-01767-4 | ||
| 003 | DE-He213 | ||
| 005 | 20240730165141.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 220601s2020 sz | s |||| 0|eng d | ||
| 020 |
_a9783031017674 _9978-3-031-01767-4 |
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| 024 | 7 |
_a10.1007/978-3-031-01767-4 _2doi |
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| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
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| 072 | 7 |
_aTEC008010 _2bisacsh |
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| 072 | 7 |
_aTJFC _2thema |
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| 082 | 0 | 4 |
_a621.3815 _223 |
| 100 | 1 |
_aKrishna, Tushar. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _987633 |
|
| 245 | 1 | 0 |
_aData Orchestration in Deep Learning Accelerators _h[electronic resource] / _cby Tushar Krishna, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Ananda Samajdar. |
| 250 | _a1st ed. 2020. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2020. |
|
| 300 |
_aXVII, 146 p. _bonline resource. |
||
| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
||
| 490 | 1 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 |
|
| 505 | 0 | _aPreface -- Acknowledgments -- Introduction to Data Orchestration -- Dataflow and Data Reuse -- Buffer Hierarchies -- Networks-on-Chip -- Putting it Together: Architecting a DNN Accelerator -- Modeling Accelerator Design Space -- Orchestrating Compressed-Sparse Data -- Conclusions -- Bibliography -- Authors' Biographies. | |
| 520 | _aThis Synthesis Lecture focuses on techniques for efficient data orchestration within DNN accelerators. The End of Moore's Law, coupled with the increasing growth in deep learning and other AI applications has led to the emergence of custom Deep Neural Network (DNN) accelerators for energy-efficient inference on edge devices. Modern DNNs have millions of hyper parameters and involve billions of computations; this necessitates extensive data movement from memory to on-chip processing engines. It is well known that the cost of data movement today surpasses the cost of the actual computation; therefore, DNN accelerators require careful orchestration of data across on-chip compute, network, and memory elements to minimize the number of accesses to external DRAM. The book covers DNN dataflows, data reuse, buffer hierarchies, networks-on-chip, and automated design-space exploration. It concludes with data orchestration challenges with compressed and sparse DNNs and future trends. The target audience is students, engineers, and researchers interested in designing high-performance and low-energy accelerators for DNN inference. | ||
| 650 | 0 |
_aElectronic circuits. _919581 |
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| 650 | 0 |
_aMicroprocessors. _987635 |
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| 650 | 0 |
_aComputer architecture. _93513 |
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| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _987637 |
| 650 | 2 | 4 |
_aProcessor Architectures. _987638 |
| 700 | 1 |
_aKwon, Hyoukjun. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _987640 |
|
| 700 | 1 |
_aParashar, Angshuman. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _987641 |
|
| 700 | 1 |
_aPellauer, Michael. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _987642 |
|
| 700 | 1 |
_aSamajdar, Ananda. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _987644 |
|
| 710 | 2 |
_aSpringerLink (Online service) _987647 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031000645 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031006395 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031028953 |
| 830 | 0 |
_aSynthesis Lectures on Computer Architecture, _x1935-3243 _987648 |
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| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-031-01767-4 |
| 912 | _aZDB-2-SXSC | ||
| 942 | _cEBK | ||
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_c86128 _d86128 |
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