| 000 | 03835nam a22006495i 4500 | ||
|---|---|---|---|
| 001 | 978-3-030-43243-0 | ||
| 003 | DE-He213 | ||
| 005 | 20240730173117.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 200509s2020 sz | s |||| 0|eng d | ||
| 020 |
_a9783030432430 _9978-3-030-43243-0 |
||
| 024 | 7 |
_a10.1007/978-3-030-43243-0 _2doi |
|
| 050 | 4 | _aQA76.6-76.66 | |
| 072 | 7 |
_aUM _2bicssc |
|
| 072 | 7 |
_aCOM051000 _2bisacsh |
|
| 072 | 7 |
_aUM _2thema |
|
| 082 | 0 | 4 |
_a005.11 _223 |
| 100 | 1 |
_aLutsyk, Petro. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _9106940 |
|
| 245 | 1 | 2 |
_aA Pipelined Multi-Core Machine with Operating System Support _h[electronic resource] : _bHardware Implementation and Correctness Proof / _cby Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul. |
| 250 | _a1st ed. 2020. | ||
| 264 | 1 |
_aCham : _bSpringer International Publishing : _bImprint: Springer, _c2020. |
|
| 300 |
_aXV, 628 p. 1 illus. _bonline resource. |
||
| 336 |
_atext _btxt _2rdacontent |
||
| 337 |
_acomputer _bc _2rdamedia |
||
| 338 |
_aonline resource _bcr _2rdacarrier |
||
| 347 |
_atext file _bPDF _2rda |
||
| 490 | 1 |
_aTheoretical Computer Science and General Issues, _x2512-2029 ; _v9999 |
|
| 505 | 0 | _aIntroductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic. | |
| 520 | _aThis work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) • I/O-interrupt controller and a disk . | ||
| 650 | 0 |
_aComputer programming. _94169 |
|
| 650 | 0 |
_aComputer engineering. _910164 |
|
| 650 | 0 |
_aComputer networks . _931572 |
|
| 650 | 0 |
_aMicroprogramming . _932081 |
|
| 650 | 0 |
_aComputer input-output equipment. _922942 |
|
| 650 | 0 |
_aLogic programming. _92730 |
|
| 650 | 0 |
_aComputer science. _99832 |
|
| 650 | 1 | 4 |
_aProgramming Techniques. _9106941 |
| 650 | 2 | 4 |
_aComputer Engineering and Networks. _9106942 |
| 650 | 2 | 4 |
_aControl Structures and Microprogramming. _932083 |
| 650 | 2 | 4 |
_aInput/Output and Data Communications. _937326 |
| 650 | 2 | 4 |
_aLogic in AI. _933012 |
| 650 | 2 | 4 |
_aTheory of Computation. _9106943 |
| 700 | 1 |
_aOberhauser, Jonas. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _9106944 |
|
| 700 | 1 |
_aPaul, Wolfgang J. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _9106945 |
|
| 710 | 2 |
_aSpringerLink (Online service) _9106946 |
|
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030432423 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783030432447 |
| 830 | 0 |
_aTheoretical Computer Science and General Issues, _x2512-2029 ; _v9999 _9106947 |
|
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-030-43243-0 |
| 912 | _aZDB-2-SCS | ||
| 912 | _aZDB-2-SXCS | ||
| 912 | _aZDB-2-LNC | ||
| 942 | _cELN | ||
| 999 |
_c88740 _d88740 |
||